question on Verilog coding

[shrikanthke]

Hi,

I created a memory using command "reg [15:0] memory_bank[3:0];". How to initialise this memory with come values ?

 

[sharath666]

Use a for loop...

 

[shrikanthke]

Thanks Sharath. i used initial block in that module.

One more question.. I used a inout signal in one module. Now im calling that module from another module. I want to instantiate that module(which uses inout signal). here is my code.


Logic_Controller M2(.logic_controller_enable(logic_controller_enable),.input_to_lc(input_type),.read_enable(read_enable),.write_enable(mem_write),.CLK(CLK),.bus_lc(bus));
Memory M3(.mem_read(mem_read),.mem_write(mem_write),.CLK(CLK),.bus(bus));

here bus_lc and bus are inout signals. When i try to synthesize this, im getting error as "Multiple drivers are connected".

 

[ads-ee]

here bus_lc and bus are inout signals. When i try to synthesize this, im getting error as "Multiple drivers are connected".

Because you have multiple drivers bus_lc and bus are both driving bus.

An inout port should only be used for pins on a device. Unless there is a library component for building up tristate buses internal to your ASIC, you can't drive multiple outputs onto the same wire. Regardless if such a internal tristate driver library component existed, I would still avoid using such a component.

I only know of one chip vendor that built something like that into their devices (Xilinx) and I'll tell you the device could easily overheat/be_damaged when multiple drivers were driving different values on those tristate buses. I recall being brought onto a project to fix a design that didn't ensure that all drivers were mutually exclusive and did not overlap their enables under any circumstances, the part go so hot you couldn't touch it.

 

[shrikanthke]

Thanks.

So, inout ports can be used inside one module . And it cannot be used in between two devices. is it correct ?

 

[ads-ee]

You shouldn't use inout unless the port is a pin on a package on the ASIC. And if you use it you better make sure the output is tristateable, otherwise you can never use it as an input.

The synthesis error you were seeing was likely due to the lack of an internal tri-state buffer for the ASIC library you are using.

You can use inout between two devices that are instantiated in a testbench, which is for simulation only. If you don't correctly handle the tri-states you'll end up with Xs on the bus.