Randomication in verilog

[shrikanthke]

HI,

i want to use random function in verilog HDL. i will have a set of numbers(6-8 in number) from which a random number has to be selected every time. suggest me the ways of implementing it.

 

[kam1787]

Not sure I understand.

you have set of numbers and you want to select one of them at random? Repeats are allowed?

 

[mrflibble]

Question: Is this for synthesis (use in real hardware)? Or is this just for simulation?

If it's for simulation: use one of many $randomthingy constructs available in the language.

If it's for synthesis: you can use something like a LFSR: http://en.wikipedia.org/wiki/Linear_feedback_shift_register

For an easy start on the use of LFSRs, see this generator: http://outputlogic.com/?page_id=275

There's also a big table in a Xilinx app note by Peter Alfke. Let's see if I can find the link...

This one: http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf

Oh yeah, if this is verilog and the randomization is purely for simulation, then you might want to use SystemVerilog for your testbench. SV has a lot more random goodness compared to the older verilog standard. So if you use lets say Modelsim, then you should be good to go.