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vsim-pli-3691
I use the system task $random in my design, like:
a_in = {$random(0)};
there is no error of compiling, but when simulating, there is an error:
Error: (vsim-PLI-3691) : Expected a system task, not a system function '$random'.
anyone could help me to fix this problem?
thanks.
Thank you for your reply.
Yes, the cache I mean is build-in the arm process. Since there are no specific I/O for the arm process, everytime I write data outside of the process, like to fifo, it seems that the data will be first written to dcache, and then written out. If I try to write out the...
hi, I have a question about the delay implementation in chip design.
It's easy to implement in verilog for simulation, but how can it be implemented in real chip?
using flip-flop? how about the "delay 0" ?
does anyone use ARM processor series?
If you do, could you tell me what is the relationship between the cache and the memory of the ARM processor, is it write through or write back?
I am totally confused.
Thanks
Re: anyone have ideas about the memory design in silicon ens
Thanks for the reply
ARTISAN has the memory generator which can generate SRAM, ROM and Registerfile
Added after 2 minutes:
The version of LEF file of memory is 5.2, which should be able to be run at silicon ensemble.
also the...
I use ARTISAN to generate RAM, and get the LEF file. But it doesn't work well.
The tool is silicon ensemble. I import the LEF file of cell library first, and then import the LEF file of memory, It always said "Invalid token here OR missing space between token and ":""
It drives me crazy.
verilog and VHDL
What is the difference between these two? which one is useful or popular?
verilog HDL means verilog or vhdl?
it might be a stupic question, but thanks for your answer.
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