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I think the iprobe component could not be used to test fully differential loop gain and phase. You can insert large ind, eg 1GH in the feedback path, and use AC coupling capacitor to set AC input signal. The iprobe component can be used to test loop gain and phase when the feedback is at a...
Re: How to plot MOSCAP C-V curve using Cadence Spectre in AD
for moscap, C-V fullfill the formular: V=I*Z=I/(jwc) , so |C|=|I/(w*V)|
if V=1,w=1 then C=I
Insert a dc voltage source in the gate of moscap, set the "ac amplitude" to 1 and dc voltage to "Vin". Do ac simulation and sweep the...
Hi,everyone
I've got some questions about cmfb stability in two-stage op amplifier.
1） Figure 1 is a schematic of two-stage opa with continuous cmfb circuit. I insert a device of iprobe (in analogLib library) to simulate the loop gain and phase of cmfb circuit. Figure 2 shows a voltage buffer...
I'm now designing on if filter of fc=50M BW=20M. Gm-C architecture is used in my design. We all know the center frequency is depend on the value of gm/c. To save current of the filter, gm should not be chose too large. So the value of C is chose to less than 1pF. The question is a variation of...
Thanks!
But according to the circuit, the output of the second stage has been already changed. This topology is some type of modified two-thomas filter.
I have designed a two-thomas filter with a bandpass ouput. The architecture of the filter and opamp can be found in the attachment. The problem is when I simulate the loopgain and phase of the first loop as the way in the attachment, the initial phase of is 0 rather than 180. It seams that the...
I have met some problems in using MIMCAP of tsmc18rf with ADS2008.
If I select the MIMCAP component, ADS will shut down automatically.
The same problem will occur in ADS2006.
How to solve this problem?
I have met some problems in using MIMCAP of tsmc18rf with ADS2008.
If I select the MIMCAP component, ADS will shut down automatically.
The same problem will occur in ADS2006.
How to solve this problem?
corners simulation
Hi,
Make sure you simulate opamp with the cmfb circuit and current mirrored bias curcuit. Check the operation region of the tail curret mosfet.
I am now doing whole chip post-simulation, and I meet a convergence problem.
We use calibre to extract calibreview for hierarchy simulation(LVS done). It contains about 900,000 devices(mosfets and parasitic res and cap). The log file of the simulation with spectre shows an error of...
We are now doing mixed signal layout lvs. The digital circuit is described with verilogHDL, while calibre can only recongnize cdl netlist. How can I deal with this lvs problem? How can I translate verilogHDL to spice netlist?
Thanks a lot!
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