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How to solve the convergence problem in post simulation?

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sharpsheep

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I am now doing whole chip post-simulation, and I meet a convergence problem.

We use calibre to extract calibreview for hierarchy simulation(LVS done). It contains about 900,000 devices(mosfets and parasitic res and cap). The log file of the simulation with spectre shows an error of
//Error found by spectre during DC analysis, during info [finalTimeOp].Analysis skipped due to inability to cimpute operating point /.....

The same error occurs when I use a calibreview which contains no paracitic devices. However, there is no error when I use schematic to simulate.

Please help me with the problem. Thanks very much!
 

bicave

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Non-convergence is the normal problem in IC simulation.
- If it has ocilator, you must run with small step.
- VDD need time to wake up ex: PWL(..)
- Check carefully no floating input signal
- FF need initial condition with .IC statement

May be cause by division by Zero.
 

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