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Recent content by shankarmit

  1. S

    SOC Encounter - request for resources

    Re: SOC Encounter u can find sample design and library in learning.cadence.com register and try for internet learning module. Thanks Shankar
  2. S

    estimation of gate count

    U can get total standard cell are using DC report_area command. Then u take area of a nand gate, and divide it to get approx gate count. Thanks Regards Shankar
  3. S

    using astro2004 for 2007 lab

    did u do scan trace before detaching the scan chain.. Try axgScanTrace command.
  4. S

    How to read all the cells in .db library using Design Compiler?

    Re: reading a library U can usee read_lib command and load your design.
  5. S

    Creating LM view for reference library

    Hi nehar, Let me know in detail what issue u have, u should .db in your reference design. and it will create LM view.. Thanks Regards Shankar
  6. S

    Creating LM view for reference library

    astro lm view yes u r right. u need to create LM view for ur reference designs. Load ur .db file using Librrary Preparation-->CreateLogicalview Thanks Shankar
  7. S

    using astro2004 for 2007 lab

    Hi, Slack shows 10,000 when u dont load SDC properly. Check ur log for ataLoadSDC outputs any error.
  8. S

    a APR problerm of Synopsys Astro

    Then u need to do either of this, The technology file .tf must a have section TILE check that u change the name unit to unitTile_1. or Rename the cell as UnitTile using geSaveAs command. Thanks Regards Shankar
  9. S

    a APR problerm of Synopsys Astro

    synopsys astro Hi, Check ur reference standard cell lib has unitcell in it.. If not used auSetPRBrdy and create unit cell. Thanks Regards Shankar
  10. S

    How to do power planning?physical-designers please address.

    Re: How to do power planning?physical-designers please addre Hi deh, Refer this document for powerplanning..
  11. S

    Libraries for I/O and power pads

    Re: I/O and power pads Hi ravi, Yes, there is separate library for i/o pads and power pads... For example.. tsmc will have library tpz... something like that for pad library.. Check with ur vendor.. Thanks shankar
  12. S

    wht is theory behind floating pins

    One more thing to be noted..u need not leave floating inputs to be left... u should tie high or tie low the inputs..If u leave inputs floating noise may tigger it and affect logic and power consumption too.. Shankar
  13. S

    How to import Cadence rule deck format to Synopsys?

    Re: rule deck format YA fab guys will release different rule deck for various eda companies.. i have separate run deck for cadence,synopsys.. I think there is no generator like that to convert one edatool format to another edatool format.. but can write rule deck urself according to the tool u...
  14. S

    Problem with configuring divided clock that uses flip-flop in CTS

    Re: CTS Problem !!! Help When a flop Q pin is declared as clock clk2 then the clock clk1 of the fliplop will propagate thats why u will get problems. U can declare a ignore pin or stop pin and do cts for clock clk1. Then do for clk2 separetly... This problem occurs when u design divider...
  15. S

    could someone help me for cts of astro?

    1.. For doing CTS is reset, astCTS will work only for clock nets.. U can use astHFCTS (highfanout cts) and give the reset nets.. Added after 4 minutes: 2.... astro CTS assumes.. the input pin of and gate as stop point (sink pin) since u declared clock on the output port of that and gate...
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