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First of all if X-axis has to be time, then perform transient analysis (not ac analysis). Probe the node (drain of MOS), and not the net. You might be probing the net hence output is in voltage.
Re: AMS simulation problem
For getting good grip on AMS simulation, the only way out is doing more simulations. there are lot of issues as the tools are not mature enough...........for each of the problems you face raise a query with the tool vendor.........they should solve it........and yes...
Re: AMS simulation problem
you have to give some more information. It is diffcult to debug from this much information.
One possible reason can be that during elaboration phase it is looking for some behavioral file which might be deleted or moved. This is just a guess.
Hi,
I am using rectangular window for converting a time domain signal to frequency domain.
Now, for finding SNR, do I need to subtract DFT processing gain from the final expression.
I mean, does rectangular windowing cause any DFT processing gain????
Best Regards
Sarfraz
Hi All,
Is it possible to declare an analog output array of a block/
For example
module XYZ (a,b);
output [Array_size-1:0] a;
Now how to declare this output a net i.e whether to use wreal or electrical or is there any other assignment.
The port a is supposed to carry analog...
Thats true that the tools give us the results even if we put ac as 1V.
However theoritically speaking these high value of small signal ac can cause problem, and there can be error in the final results.
Sarfraz
Re: CMOS
hey u are asking about NMOS and PMOS or nwell and pwell process?
It is not true that nwell process are preferred over pwell processes. It depends upon the particular design and architecture implementation
Re: CMOS
it is because mobilityt of electrons is more than hole.
So it gives more current carring capabiltiy for NMOS as compared to PMOS.
There are other things also, you can refer to any book on CMOS
regards
Sarfraz
Re: why do transistors with same W/L have different performa
these effects are basically because of two effects
Wide channel or long channel effects (90%)
Haloe effect (10%)
regards
Sarfraz
Most of the tolls use iterative methods such as newton raphson method to arrive at solution.
For Newton Raphson methods to converge it requires to meet certain conditions.
Most of the convergence problems are seen for dc and transient analysis
regards
Sarfraz
Hi,
We set ac=1V only to make the calculations simple for ourselves.
i.e ac analysis is done primarily to find the loop characterisitcs.
Gain = 20 log (Output/Input )
If input equal to 1, then gain is 20log (output).
However one question still remains:
ac analysis is a small signal...
Hi,
In PLL frequency sysnthesizers, we require programmable Divide by N counters.
I need some architecture for programmable divide by N counter.
Can anybody forward some documents/notes/book on this topic.
Regards
Sarfraz
I am new to PLL design.
Can anybody tell me what are the different types of PLL like fractional PLL, integer PLL , Sigma Delta PLL.
Can anybody give some brief details of these things
Regards
Sarfraz
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