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Doubt Related to Verilog AMS

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shaikhsarfraz

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Hi All,
Is it possible to declare an analog output array of a block/

For example

module XYZ (a,b);

output [Array_size-1:0] a;

Now how to declare this output a net i.e whether to use wreal or electrical or is there any other assignment.
The port a is supposed to carry analog signals.

Regards
Sarfraz
 

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