Programmable Divide by N Counter

[shaikhsarfraz]

Hi,
In PLL frequency sysnthesizers, we require programmable Divide by N counters.

I need some architecture for programmable divide by N counter.

Can anybody forward some documents/notes/book on this topic.

Regards
Sarfraz

 

[rficd]

you can refer to razavi's book about PLL. the main theory of N divider is formed by A counter ,B counter and one dual mode prescaler DMP(p/p+1). assumed that the vaule of A and B counter are A and B, respectively, and A>B. A and B is counted at the same time. when B <=0, the DMP divider p+1. after B=0, the DMP divide p until to A =0. then, A and B counters reset. as a result, the divider number N is equal to A*p+B.

Added after 3 minutes:

sorry, there is one typo. Please read as follow:

you can refer to razavi's book about PLL.
the main theory of N divider is formed by A counter ,B counter and one dual mode prescaler DMP(p/p+1). assumed that the vaule of A and B counter are A and B, respectively, and A>B. A and B is counted at the same time. when B >=0, the DMP divider p+1. after B=0, the DMP divide p until to A =0. then, A and B counters reset. as a result, the divider number N is equal to A*p+B.