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Recent content by sethtalk

  1. sethtalk

    Question about "A 10bit 320MS/s Low-Cost SAR ADC for IEEE 802.11ac" jssc 2015

    in high speed sar design, redundancy technique is usually used in CDAC architecture, but it always has "one-sided tolerance of dynamic conversion errors" (paper2) , however , in paper1 , the author not mentioned this issue, do every who understand this paper can give a command? paper1: A...
  2. sethtalk

    Comparator gain question for high speed SAR

    Re: comparator gain question for high speed sar hi,dick_freebird, your reply help me a lot, thanks! (IOS : i means input offset cancellation ...) i think a conclusion: latch comparator gain is infinite , the key is speed, that is why we always need some pre-amplifier stages to boost LSB...
  3. sethtalk

    Comparator gain question for high speed SAR

    comparator gain question for high speed sar hi, in traditional low speed high resolution sar adc, the comparator adopt OOS or IOS pre-amplifier stages to boost comparator gain and then it can meet high resolution requirement, but i find papers which is about high speed(10b or more) sar...
  4. sethtalk

    question about TSMC 0.13um PDK symbol

    hi, i use tsmc 0.13um PDK and make an inverter ckt & symbol, the MOS W/L is defined by parameter method (ex: L = pPar("lp"),...) it displays like " 1e-6/130e-9" instead of 1u/0.13u , do somebody know how to correct make an symbol , which show W/L value in "u", not in "e-6" (PS: in tsmc...
  5. sethtalk

    [ESD question]do a cmos swith which connected to PAD should obey ESD rule?

    leo_o2: i forget to say that i can't use a series resistor connect to the switch,it will degrade analog performance,
  6. sethtalk

    [ESD question]do a cmos swith which connected to PAD should obey ESD rule?

    but if the small swith pass some ESD current, it represent the high impedance node (it connect to op input) have leakage path, ie some device is die??
  7. sethtalk

    [ESD question]do a cmos swith which connected to PAD should obey ESD rule?

    dear sir: recently i design a switched-capacitor circuit in tsmc 0.18um, in the circuit a CMOS transmission gate connect to PAD and an OPAMP input (high impedence), the switch size is << ESD protection mos in PAD, do the small swith need obey ESD rule? for example, enlarge contact to poly...
  8. sethtalk

    Mismatch parameters TSCM 90nm

    hi,matko: recently i prepare to design a 10b current-steering DAC and i am looking for estimate Avt,Abeta too, could you tell me the paper you mentioned above (formula of Avt), tks!!
  9. sethtalk

    how to extract Avt,A(beta) in palgrom mismatch model

    how to extract Avt,A(beta) in pelgrom mismatch model i want to calculate current mirror mismach using pelgrom model, do someone know that use mismatch model (provide by foundry) to extract Avt, Aβ parameter PS:i have tsmc 0.16um spice model (not PDK)
  10. sethtalk

    PADC design problems ,could you pls help me?

    all your question can be find in the follow book Data Converters, FRANCO MALOBERTI , Springer Springer - International Publisher Science, Technology, Medicine
  11. sethtalk

    Mismatch parameters TSCM 90nm

    it help me,tks!!
  12. sethtalk

    find a suitable instrument for a 12b ADC sinewave input

    recently i want to measure a 12b/30MSPS adc performance, cold sombody give me a suggention that what instrument suitable for the adc? i have an Agilent 33250A AWG (arbitrary wave generator) in hand, but the i con only probide -60dBc harmonic distortin ,it seems not enough for 12 abc.
  13. sethtalk

    [question]".sample" command in hspice to cal. samp

    Re: [question]".sample" command in hspice to cal. hi erikl: i upload the complete netlist/spice/model. tks!!
  14. sethtalk

    [question]".sample" command in hspice to cal. samp

    hi,erikl: thanks for you reply,in fact,i do write 300meg, and the AC simulation is sucessful and the .ac file generated , but in the .lis file, it shows the sampled output noise power =0,

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