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Has anyone tried flipping the bandgap reference circuit, meaning diodes on top and resistors on bottom. Traditionally, resistors are on top and diode pair is at the bottom connected to ground. Anyone know the advantages of this structure ?
Thanks for your reply, now it makes more sense. I am guessing you are taking the 2nd pole listed in the output. What about the first one which is @ -3.597314e+04 0. -5.725302e+03 0. ?
I want to learn .PZ analysis in hspice and in order to do so I created a simple testbench for a RC circuit:
R1 A B 1k
C1 B 0 1n
Vpz A 0 DC 1 AC 1
.PZ V(B) Vpz
I expect the pole to be at 1MHz but spice gives me extremely weird results:
poles (rad/sec) poles ( hertz)
real...
I am seeing an condition in my simulation where the PMOS gate is higher than n-well. Can this cause a potential problem ? S/D are however lower than n-well.
Hi ee171, Thanks a ton for the upload! I have been searching for these since a long time, however I looked at the lectures and could not find lectures 4, 6, 17, 18. Could you double check if those got uploaded ?
Thanks once again ! Cant express how much I appreciate this!
Thanks ee171 for giving us back these good old lectures. Although I just find first two lectures as of now. Can you please upload the rest of the lectures as well ? Thanks in advance!
I have read in books that for better matching of current mirrors, it is better to have them laid out in same direction such that current always flows in the same direction for both the mirror devices. However, I am not sure how that would improve matching in mirror ? Would appreciate your...
I understand that when two transistors W/L=2/1 are connected in series then they act like a transistor of size 2/2. But what would happen if I connect two transistors in series, first one being 2/1 and second one being 2/2. What is the equivalent dimension in this case?
I was looking at simple way to find Vt of a NMOS transistor, I figured, I could apply vdd on the gate and vdd on the drain and see the source dc level. So whatever the source dc level minus vdd is the Vt of the cell. Am I doing something wrong here ?
Just to cross check, I did a DC simulation...
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