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Hello All,
Does RTL design will contain flip flops... or does the RTL synthesized netlist will only have flops... ?? Can you please elaborate.... ??
Thanks!
Satish
It's got to do with the active edge..... why are hold checks done at the same edge...while setup checks done at consecutive edges... ?? Can someone please explain ??
Sorry for the confusion.... it's not setup time but setup violation.
Let me reframe the question....
When setup violation occurs we remove it by reducing the frequency or increasing the time period...
Why is that the case ??
Hi,
Suppose I have an ASIC which runs at 4Ghz clock and at a particular voltage... I increase the frequency to 6Ghz....why do I have to increase the voltage.... ?? can someone please explain the relationship between operating frequency and voltage... ??
Thanks!
Satish R
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