Does RtL design will contain flops ??

[sara1983]

Hello All,
Does RTL design will contain flip flops... or does the RTL synthesized netlist will only have flops... ?? Can you please elaborate.... ??

Thanks!
Satish

 

[dpaul]

@sara1983 ,
Does RTL design will contain flip flops...
-- An RTL has the description in a high level language(VHDL/Verilog) that represents the behavior of a flop.

or does the RTL synthesized netlist will only have flops... ??
-- Look up the definition of a "netlist"!

Search - "difference RTL and netlist"

I leave it as an exercise for you, the answers are easy to find out!