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Why does Setup time of a flipflop depend on frequency ??

sara1983

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Hi,
Can someone please explain why setup time of a flipflop depends on frequency....of the clock....??

Thanks!
Satish
 

KlausST

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Hi,

I'm unsure what you are talking about. Maybe it's the other way round.

--> please give some context, best a link to an according document.

Klaus
 

sara1983

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Let me reframe the question....

When setup time occurs we remove it by reducing the frequency or increasing the time period...
Why is that the case ??
 

dick_freebird

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There could be a correlation between setup time
and max toggle across technologies.

As you approach the max clock capability there's
a good chance that some nodes are not fully
settled and so setup time might change slightly.
But I'd expect this only to apply to "edgy"
ranges, not a proportionality across decades
of clock frequency.
--- Updated ---

Let me reframe the question....

When setup time occurs we remove it by reducing the frequency or increasing the time period...
Why is that the case ??
You are not changing the required setup time.
You are changing the actual time you gave it,
to encompass that required setup time, by
making the period longer than the inter-register
logic that is the source of the lag.
 

sara1983

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Sorry for the confusion.... it's not setup time but setup violation.
Let me reframe the question....

When setup violation occurs we remove it by reducing the frequency or increasing the time period...
Why is that the case ??
 

FvM

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The problem is about understanding how synchronous logic works (copied from Synopsys Timing Constraints and Optimization User Guide)

1635065339737.png

In Figure 1-1, the dashed arrow represents a timing path. The change in signal data caused by a clock transition at flip-flop FF1 must be propagated to flip-flop FF2 before the following clock edge arrives at FF2, so that the logically processed data can be reliably latched into FF2. The change at FF1.Q might affect the output of the combinational logic cloud at FF2.D, depending on the logic itself, the data value, and the values of any side inputs feeding into the logic. The change at FF2.D, if any, must occur before the next clock edge arriving at FF2.

1635065514118.png


Figure 1-2 shows the timing for this path. The arrival of a clock edge at FF1 latches the data at the input FF1.D into the flip-flop. It also places that data on the flip-flop output, FF1.Q, after the clock-to-Q delay of the flip-flop. This is called the launch event for the timing path.

This signal goes through the combinational logic with some delay. The output of the combinational logic is at the input of the second flip-flop, FF2.D. The time at which the signal value changes here is called the arrival time for the path.

The change in value at FF2.D must occur before the arrival of the clock edge arriving at FF2, by at least an amount equal to the setup time requirement for the flip-flop. This latest allowable arrival time is called the required time for the path. The latching of data at FF2 is called the capture event for the timing path. In this example, the capture event occurs one whole clock cycle after the launch event.

The amount of time by which the timing constraint is met is called the slack of the timing check. If the signal arrives earlier than necessary as shown in Figure 1-2, the slack is positive. If the signal arrives exactly at the required time, the slack is zero and the timing constraint is barely met. If the signal arrives later than the required time, the slack is negative. In all three cases, the amount of slack is the required time minus the arrival time. For example, if the required time is 1.8 ns after the launch clock edge and the arrival time is 1.6 ns after the launch clock edge, the slack is 1.8 minus 1.6, or 0.2 ns, a positive number.

The preceding timing check is called a setup check, which verifies that a change in data arrives soon enough before each clock edge at the sequential device. This is the most common type of timing check that drives synthesis and optimization. However, other types of timing checks can be performed as well.
 

sara1983

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It's got to do with the active edge..... why are hold checks done at the same edge...while setup checks done at consecutive edges... ?? Can someone please explain ??
 

FvM

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I could continue with retelling respective documents, e.g. said Synopsys Timing Constraints and Optimization User Guide. However, that's basic logic design stuff, why not read the documents yourself? You can come back if you have additional questions.
 

dpaul

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@sara1983
Yet another question re-frame suggestion for you from my side: :)
"Please point me to freely available documents/atricles where I can read about and understand about setup and hold time violations".
 

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