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1.Does these ROM and RAM need to be codded as a separate module .........i.e. if i have a RAM of 2K is it strict to be placed as a separate module or i can use them in my already existing module with another always block......
2.if i have a RAM within in the module as another always block how...
i need to have memory in my design is it possible to have internal memory of some 10K in fpga or we need to have only external memory ........i am using xilinx version 8.1i and the device i choose is virtex - II pro xc2vp7 which has the 11,088 logic cells
792 BRAM(Kbits) 44 (18X18)...
1.The reason is to keep the data that is to be read from external memory internally and process it.....instead of going to external memory each time...so we can reduce clocks........
2.Is this process which i described can be used without any back end problems......
1.i have internal memory in my design which is filled in with the data from the external memory.....this process is done in an always block
2.after filling in the internal memory with data..... there is an another always block which will be refreshing the internal memory ......i.e the data...
1.i need to enable module2 from module1 and.....after finishing some operation i need to disable the module2 from processing .....and continue the manipulation in module1
2.i tried like giving an enable signal [en_1 o/p from module1] from module1 to module2 such that if that enable signal is...
Re: foldering in c++
#include <stdlib.h>
int main()
{
int i;
for(i=0;i<10;i++)
{
system ("mkdir %d",i);
}
}
1.i need to create many folder each name depending on variable is it possible to create with the above code
2.can u suggest me some metod to create many folders
the above...
1.is it possible to asses memory in an combinational always block like this
always@( a or b or c or d)
begin
addr=a+1;
if( r[addr] == 0)
begin
e=a-3;
end
end
2.in this always block the sensitive list doesnot contain the addr which will be generated in the always block only
3.is it right way of...
always block verilog
1.is it possible to asses memory in an combinational always block like this
always@( a or b or c or d)
begin
addr=a+1;
if( r[addr] == 0)
begin
e=a-3;
end
end
2.in this always block the sensitive list...
i.i need a help on how to write a industry standard testbench for my project i
2.Is there any e books available or some other materials what is the standard procedure to be followed
can we have macros as we have in c in verilog too if so how to implement it i have tried to implement using define ...is it good way or any other better way is available
i.e.
macro(x,n) x & n
bit =macro(x,n)
case within case
1.can we use a case statement within a case statment like the one described below
e.g.
case(state2)
1:begin
case(state1)
1:begin
end
2:begin
end...
morris mano digital electronics free download
"digital logic design" by charles roth is good book for counter designs and sequential circuits
DIGITAL DESIGN BY marcovitzis new to the market and it is good one
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