# How to implement macros in Verilog?

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#### samuel_raja_77

##### Junior Member level 2
can we have macros as we have in c in verilog too if so how to implement it i have tried to implement using define ...is it good way or any other better way is available
i.e.
macro(x,n) x & n

bit =macro(x,n)

#### s_vlsi

##### Junior Member level 2
Re: macro in verilog

According to me .In verilog it is only through 'define

According to me .In verilog it is only through 'define

#### shiv_emf

macro in verilog

yes ...define is keyword which is used as MACRO in VERILOG

#### samuel_raja_77

##### Junior Member level 2
Re: macro in verilog

IS define synthesizable and what about the usage of parameter instead of define

#### bansalr

##### Full Member level 3
Re: macro in verilog

The difference between define and parameter is define can be used as global defination in a seperate file which can be included.
Also the parameter can be changed while instatatiation while defines cannot.

Both are synthesizable as it is just a method of constant selction provided by the language construct.

Defines are best used for verilog code written for reusability.

#### nand_gates

Re: macro in verilog

Here is an example! Yes macros are synthesizable! for more info see
"19.3 define and undef " form ieee1364-2001 doc.
Hope this helps!
Code:
define m_and(x, n) x & n
module my_and (a, b, y);
input a, b;
output y;
assign y = m_and(a,b);
endmodule // my_and

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