Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to implement macros in Verilog?

Status
Not open for further replies.

samuel_raja_77

Junior Member level 2
Joined
Apr 8, 2006
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,458
can we have macros as we have in c in verilog too if so how to implement it i have tried to implement using define ...is it good way or any other better way is available
i.e.
macro(x,n) x & n

bit =macro(x,n)
 

s_vlsi

Junior Member level 2
Joined
May 16, 2006
Messages
20
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,283
Activity points
1,460
Re: macro in verilog

According to me .In verilog it is only through 'define

Added after 20 seconds:



According to me .In verilog it is only through 'define
 

shiv_emf

Advanced Member level 2
Joined
Aug 31, 2005
Messages
605
Helped
22
Reputation
44
Reaction score
6
Trophy points
1,298
Activity points
4,106
macro in verilog

yes ...define is keyword which is used as MACRO in VERILOG
 

samuel_raja_77

Junior Member level 2
Joined
Apr 8, 2006
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,458
Re: macro in verilog

IS define synthesizable and what about the usage of parameter instead of define
 

bansalr

Full Member level 3
Joined
Dec 22, 2005
Messages
152
Helped
20
Reputation
40
Reaction score
5
Trophy points
1,298
Activity points
2,165
Re: macro in verilog

The difference between define and parameter is define can be used as global defination in a seperate file which can be included.
Also the parameter can be changed while instatatiation while defines cannot.

Both are synthesizable as it is just a method of constant selction provided by the language construct.

Defines are best used for verilog code written for reusability.
 

nand_gates

Advanced Member level 3
Joined
Jul 19, 2004
Messages
892
Helped
175
Reputation
350
Reaction score
51
Trophy points
1,308
Activity points
6,830
Re: macro in verilog

Here is an example! Yes macros are synthesizable! for more info see
"19.3 `define and `undef " form ieee1364-2001 doc.
Hope this helps!
Code:
`define m_and(x, n) x & n
module my_and (a, b, y);
   input a, b;
   output y;
   assign y = `m_and(a,b);
endmodule // my_and
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top