samuel_raja_77
Junior Member level 2
can we have macros as we have in c in verilog too if so how to implement it i have tried to implement using define ...is it good way or any other better way is available
i.e.
macro(x,n) x & n
bit =macro(x,n)
i.e.
macro(x,n) x & n
bit =macro(x,n)