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Recent content by sahana

  1. S

    How can we increase clock frequency?

    How can we increase clock frequency? sahana
  2. S

    How Double Width Routes for clock nets help to avoid cross talk?

    Re: Double width Routes its double width only.
  3. S

    How Double Width Routes for clock nets help to avoid cross talk?

    Hi All, Can any body explain how Double Width Routes for clock nets help in avoiding cross talk?
  4. S

    When should we do clock shielding?

    Hi All, Can anybody inform me when to do clock sheilding? Is it after clock tree synthesis (or) after detail routing? sahana
  5. S

    Info about LVT, HVT and SVT cells and their impact on low power designs

    svt lvt ya, Iam working on 90nm.
  6. S

    Info about LVT, HVT and SVT cells and their impact on low power designs

    hvt lvt Thanks for ur replies, even i too know the same things, but i expect some what more in details other than these. sahana
  7. S

    Info about LVT, HVT and SVT cells and their impact on low power designs

    Hi can anybody attach a document regarding HVT, LVT, SVT cells and their impact in LOW Power Designs? sahana
  8. S

    Several questions relating to pins

    Hi all, Can anybody explain the answers for these questions in detail? 1.If there are too many pins of the logic cells in one place within core, what kind of issues would you face and how will you resolve? 2. As an engineer, let’s say your manager comes to you and asks for next project die...
  9. S

    How to solve clock gating violations?

    Hi, Can anybody inform me how to fix clock gating violations? Thanks, sahana
  10. S

    EndCaps & WellTaps

    Hi, Why we need to add welltaps & endcaps before placement for below 130nm designs, and we doesn't need them in above 90nm. Can anybody explain the differences in detail? thanks, sahana.
  11. S

    tcl script for IO pins

    Hi All, Can any body send me a tcl script to report all the IO pins of a block in SOC encounter using soceDBA commands? (urgent) thanks, sahana.
  12. S

    Why we need to do clock tree synthesis?

    Hi, Can any body inform me why we need to do clock tree synthesis? What happens if we don't do clock tree synthesis. Explain it in detail?
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