sahana
Newbie level 6
Hi all,
Can anybody explain the answers for these questions in detail?
1.If there are too many pins of the logic cells in one place within core, what kind of issues would you face and how will you resolve?
2. As an engineer, let’s say your manager comes to you and asks for next project die size estimation/projection, giving data on RTL size, performance requirements. How do you go about the figuring out and come up with die size considering physical aspects?
3. How will you design inserting voltage island scheme between macro pins crossing core and are at different power wells? What is the optimal resource solution?
4. Explain top level pin placement flow? What are parameters to decide?
thanks,
sahana
Can anybody explain the answers for these questions in detail?
1.If there are too many pins of the logic cells in one place within core, what kind of issues would you face and how will you resolve?
2. As an engineer, let’s say your manager comes to you and asks for next project die size estimation/projection, giving data on RTL size, performance requirements. How do you go about the figuring out and come up with die size considering physical aspects?
3. How will you design inserting voltage island scheme between macro pins crossing core and are at different power wells? What is the optimal resource solution?
4. Explain top level pin placement flow? What are parameters to decide?
thanks,
sahana