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There are two types of clock gating styles available. They are:
1) Latch-based clock gating
2) Latch-free clock gating.
Latch free clock gating
The latch-free clock gating style uses a simple AND or OR gate (depending on the edge on which flip-flops are triggered). Here if enable signal goes inactive in between the clock pulse or if it multiple times then gated clock output either can terminate prematurely or generate multiple clock pulses. This restriction makes the latch-free clock gating style inappropriate for our single-clock flip-flop based design.
Latch based clock gating
The latch-based clock gating style adds a level-sensitive latch to the design to hold the enable signal from the active edge of the clock until the inactive edge of the clock. Since the latch captures the state of the enable signal and holds it until the complete clock pulse has been generated, the enable signal need only be stable around the rising edge of the clock, just as in the traditional ungated design style.
Specific clock gating cells are required in library to be utilized by the synthesis tools. Availability of clock gating cells and automatic insertion by the EDA tools makes it simpler method of low power technique. Advantage of this method is that clock gating does not require modifications to RTL description.
The only automatic tool i know of that can fix the timing on gate-level clock gating is Azuro's PowrCentric (www.azuro.com).
Of course, you can't fix clock gate timing at the RTL level. All you can do in the RTL is force the clock gates way down the tree where they drive only a few flip flops.
A little more explanation of what is wrong with your clock gating might help.
Re: How to solve clock gating violations? even latch based doesnt seem to ignore gli?
Latch based clock gating
The latch-based clock gating style adds a level-sensitive latch to the design to hold the enable signal from the active edge of the clock until the inactive edge of the clock. Since the latch captures the state of the enable signal and holds it until the complete clock pulse has been generated, the enable signal need only be stable around the rising edge of the clock, just as in the traditional ungated design style.
Even the above method can introduce glitches, if you can check the timing diagrams clearly. So please help me if I am understanding the concept wrong.If possible someone prove that to me using timing diagrams.
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