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Recent content by ryu_hayabusa

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    Synopsys Design Compiler: Issues with "find*" and "get_*" Commands

    [UPDATE] Sorry all, I think I posted this too soon to actually notice that the get_clock command is actually giving result of "QSPI_S_CLKN" and NOT "QSPI_S_CLK". Hello all, I am curious of why we need to add the wildcard "*" at the back of a clock/cell naming, in order for the tool find it...
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    Using Synopsys Astro tdf file in IC Compiler

    Does anyone has an example of ICC's tdf file that I can refer to? I am moving from Astro to ICC, and need to reconfigure the tdf file I used in Astro, to be used in ICC.
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    "Please check your core height setting" Error when Creating Floorplan In IC Compiler

    Re: "Please check your core height setting" Error when Creating Floorplan In IC Compi Thanks again for your opinion. I have run the "check_library" command to check the libraries, and here's the output: Is it normal for standard cells lib & IO cells lib having the different tile size? For...
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    "Please check your core height setting" Error when Creating Floorplan In IC Compiler

    Re: "Please check your core height setting" Error when Creating Floorplan In IC Compi I think I found out the issue already. It seems that the IO pad cells are larger than the core area. This is due to the IO pad cells lib file is different with the std cells lib file. Can we adjust the core...
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    "Please check your core height setting" Error when Creating Floorplan In IC Compiler

    Re: "Please check your core height setting" Error when Creating Floorplan In IC Compi Thanks for your reply, my design has std cells. This is the netlist I used. It is actually a PWM signal generator, synthesized using Design Compiler: ------------------------------------------- module...
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    "Please check your core height setting" Error when Creating Floorplan In IC Compiler

    "Please check your core height setting" Error when Creating Floorplan In IC Compiler Hi, I keep getting this error when creating floorplan in ICC: ------------------------------------------------------------------------------ icc_shell> create_floorplan -start_first_row -flip_first_row...
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    Using Synopsys Astro tdf file in IC Compiler

    Hi everyone, I am planning to use a tdf file that was used in Astro, into IC Compiler. It is for the same design. Below is the Astro tdf file: ----------------------------------------------------------- define _cell (geGetEditCell) ; create power pads ; Core Power Supply insertPad "VSS"...
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    Mixed IC Design Flow Using: Synopsys DC-ICC & Cadence Virtuoso

    Hi, I am currently doing a project related to mixed IC design, for the digital part is the Digital PWM Generator Module design using verilog coding, and for the analogue part is the AC-DC & DC-DC boost converter design using Cadence Virtuoso. For the digital PWM Generator module, I am using the...
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    PWM Generator Circuit for ASIC CMOS 0.18um

    Thanks for your opinion. If that's the case, then I will just take verilog digital PWM module, run the RTL2GDSII flow then stream-in the GDSII in virtuoso instead. It will then create the mixed signal IC. Hope the foundry that will process this chip has no problem with this. Because previously I...
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    PWM Generator Circuit for ASIC CMOS 0.18um

    Hello, I am planning to use the PWM generator module in my CMOS 0.18um DC-DC boost IC design project. I will be using cadence virtuoso for my project. May I know where to find example circuit of the PWM Generators? I have been searching for it but couldn't find any. Just a simple circuit will do...
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    Syntax Error for Parameter File in Verilog format (params.vh)

    Hello, I'm using Cadence's Conformal Logic Equivalence Check tool, to run equality-check for RTL and Synthesis Netlist. I'm having problem since for the RTL golden reference part, there is one parameter file (params.vh) that is detected to have syntax error in it, thus stopping the tool's run...
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    Problem in Understanding Some Verilog Syntax

    Thanks for the fast reply kornukhin. It really helps.
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    Problem in Understanding Some Verilog Syntax

    Hello everyone, I have problems in understanding some of these verilog syntaxes: parameter ALLX_0_0 = {1{1'bx}}; Is the parameter is 1 bit or 2 bits length? And what does the {1{1'bx}} means? Is it {1{1'bx}} == 2'b1x ? ----------------------------------------------------------------- if...
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