Problem in Understanding Some Verilog Syntax

[ryu_hayabusa]

Hello everyone,
I have problems in understanding some of these verilog syntaxes:

parameter ALLX_0_0 = {1{1'bx}};

Is the parameter is 1 bit or 2 bits length?

And what does the {1{1'bx}} means? Is it {1{1'bx}} == 2'b1x ?

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if (( ~clk) === 1'bx && (cken_int == 1'b0))
begin
latched_cken = 1'b0;

What actually does the if condition means? Basically 1'bx means that it can be either 1 or 0 right?

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Pls help and Thanks in advance~

 

[kornukhin]

parameter ALLX_0_0 = {1{1'bx}};

{1{1'bx}}: 1 time 1'bx.
{2{1'bx}}: 2 times 1'bx = 2'bxx.
{2{2'b0x}}: 2 times 2'b0x = 4'b0x0x.

if (( ~clk) === 1'bx && (cken_int == 1'b0))

when you use '==' it means cken_int should be equal to 1'b0 or it can be 1'bx (not sure about 1'bz). 1'b0 == 1'bx and 1'b1 == 1'bx.

when you use '===' it means ~clk MUST be equal RHS. 1'b0 != 1'bx in this case.

Basically 1'bx means that it can be either 1 or 0 right?

Not exactly.
'==' : 'x' can be '0', '1', 'x', 'z'
'===' : 'x' is 'x' (i.e. unknown)

Hope it will help.

 

[ryu_hayabusa]

Thanks for the fast reply kornukhin. It really helps.