Syntax Error for Parameter File in Verilog format (params.vh)

[ryu_hayabusa]

Hello,

I'm using Cadence's Conformal Logic Equivalence Check tool, to run equality-check for RTL and Synthesis Netlist.

I'm having problem since for the RTL golden reference part, there is one parameter file (params.vh) that is detected to have syntax error in it, thus stopping the tool's run. But I'm not sure whether the parameter file syntax is correct or wrong. Also I'm not really sure if the (params.vh) is written in verilog or system verilog. The part that is detected for error is as below:

parameter type A_TYPE    = t_a_config;
parameter type A32_TYPE    = t_a32_config;
parameter type B_TYPE    = t_b_config;
parameter type B32_TYPE    = t_b32_config;

And the error message that I received:

Error: PARSE_ERROR: Parsing syntax error
parse error, expecting SYS_ROOT or IDENTIFIER or SELECT_NAME near token 'A_TYPE'

Are the above syntaxes are correct in terms of Verilog or SysVerilog coding?

Please help, thanks in advance.

 

[kornukhin]

'type' is SystemVerilog keyword. Do you use appropriate switch to instruct Conformal that parsed files are SV?