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Hi,
It is know that the ISI can be compensated by a time-domain channel equalizer--a linear transversal filter.
From the following paper, tt is said that "the number of adaptive tap coefficients is on the order of the number of data symbols spanned by the multipath".
For ex,
If
RMS delay...
Hi,
1.
I am not sure whether synchronous circuits are totally safe from glitches.
2.
It is said it is advisable to insert a flop to prevent glitches.
Although this flop can keep the duration of its output integral multiple clock period long, the flop may capture a WRONG value.
So , is this...
Maybe, this is a possible explanation.
But , I dont think it is like this in this case.
In the following timing path, there is still a SLICE_X62Y251.DMUX at the beginning of the path which has only ONE logic level.
Where the difference btw the 2 paths locates at is the SLICE_X63Y327.CLK with...
Re: questions of timing report(ISE) about logic levels/tas
Hi ads_ee ,
Thanks!
But it is still hard to imagine the existence of a register with a negative setup time. A negative setup time may not accord with the theory of digital circuit.
questions of timing report(ISE) about logic levels/tas
Hi ,
Could you help me?
The following timing path report is extracted from the final timing report after PAR. My expected period of clock is 4 ns. My target device is xc7v585t-3-ffg1157 (Virtex 7 family).
1.
I cannot understand...
Hi,
The DC ug tells me that "If the performance violates the timing goals by more than 15 percent, you should consider
whether to refine the design budget or modify the HDL code."
But what does this 15% stands for? Dose it mean the violation of the longest critical path is more than 15%...
one more question, plz.
What is the standard of violation for "BIG fanout"?
If the there is a fanout of 100, it is an obvious violation. But how can I judge if there is a certain fanout of 20?
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Yeah, I understand that "fanout just is number of driven gates, not any...
thanks so much
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hi hoanglongroyal ，
Thanks for your reply!
Could I ask two more questions about fanout in wireload like the following ?
wire_load("tsmc13_wl50") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 333.335...
Hi,
I wonder what the unit of fanout in technology lib is.!
I think it is not as the same as the traditional concept: the number of driven gates. The reason is as the following,
The value of fanout is used to calculate the delay. Howerver, the real delay value is derived...
Hi,
Whre can i get the timing,area,power and physical info of IOPADs?
I know that there is just some volage constrains in target lib like the following:
"
output_voltage(GENERAL) {
vol : 0.4;
voh : VDD - 0.4;
vomin : -0.5;
vomax : VDD + 0.5;
}
input_voltage(CMOS) {...
Hi,
I am confused which should be set for asynchronous control signal, false path or recovery and removal constrain?
Could you tell me how to choose and why?
Thanks!
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