Are synchronous circuits safe from glitches?

[rogeret]

Hi,

1.
I am not sure whether synchronous circuits are totally safe from glitches.

2.
It is said it is advisable to insert a flop to prevent glitches.
Although this flop can keep the duration of its output integral multiple clock period long, the flop may capture a WRONG value.
So , is this method a strong scheme?

 

[chuckey]

I think the answer is no, but they are better. take for instance if you wanted a divide by 17 circuit, this could be done by five synchronous or asynchronous binary dividers, but the end result would be that five outputs would be taken into a gate to reset the counter after a count of 17. So the output of the gate would have its own delay on the exact synchronicity of the output pulse, but with the asynchronous counter there would be an extra delay ( X5) due to the transitions through the counter stages.
Once this has occurred, extra flip flops won't re-time the wave form as the transisition would be AFTER the clock edge, while it needs to be before the clock edge by at least the set up time for that change to effect the flip flop.
Frank

 

[barry]

1) It depends. Assuming all setup and hold requirements are met, then you will not have glitches.

2) Just inserting a flip-flop guarantees you nothing. If you are thinking about adding a synchronizer to a clock-boundary-crossing situation (see metastability), that's different; then it becomes a statistical game. You can minimize metastability effects, but you can't totally eliminate them (statistically).