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in some projects' netlist, I see this subcircuit --balun,such as:
x4 vid vic v2p v2n balun
x5 vid vic vip vin balun
x6 vod voc vop von balun
who can tell me the function of balun, or its hspice netlist
Hello,everyone!
Now I know we can use the veriloga code for adc dnl and inl simulation in cadence spectre,but how to edit the veriloga code? who can help me?
my adc is 8bit 12.5Msps 1.8vpp,
spectre cadence
moisiad, have you still here?
And others,who can tell me how to compar the input ramp to the output steps to calculate the INL and DNL ?the procedure is written in what textbooks ? Because I have done the simulation as what you said above, but I don't know how to do next...
Re: how to simulate the gain and offset of dynamic comparato
Hello,renwl:
Can you tell me how to do monte carlo simulation?
And can anyone tell me how to simulate the gain of dynamic comparator
dynamic comparator introduction
hi,everyone!
I have designed a 10bit pipeline ADC, the sub-adc need many comparator as you know.I used the dynamic comparator to design it.
Now I want to know how to simulate the gain and offset of dynamic comparator?
Can anyone tell me the way...
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