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Recent content by riti

  1. R

    UPf with negative power supply volatge

    I have tried writing upf for my design using synopsys ICC2 tool. It is working fine for positive voltages but not working for negative voltages. what would be the syntax/command for making connection of negative voltage power supply through upf. In below code VBB is negative voltage...
  2. R

    Crosstalk effect on electromigtaion vilation

    Hello, if there is more crosstalk then it prone to more Electomigration violation? Is it true, if yes, Then what would be the concept behind it?
  3. R

    Inner keepout Margin while doing placement in Icc

    Hello snaulh, have you ever used inner keepout margin?
  4. R

    Clock Sinks while building clock tree during clock tree synthesis

    yes, but i forgot to mention that both upper flop and down flop are driven by clk2. Then, the clk divider (which we are assuming virtually for generating clk2) is the sink pin or not? basically i am trying to clear my concept related to sink pin and ignore pins.
  5. R

    Clock Sinks while building clock tree during clock tree synthesis

    i got your point. But if we assume, clk1 is master clock and clk2 is generated clock. then sink pins for clk2 would be Flip flop shown in picture, but what would be the sink pin for master clock (clk1 in this case)?
  6. R

    Reason of degaradation in timing violations after Clock tree synthesis

    i have worked on GPU blocks, where we have routed till 84% also.
  7. R

    Clock Sinks while building clock tree during clock tree synthesis

    Source pins of clock trees in the fanout of another clock For example, in Figure(which i have posted earlier) the source pin of the driven clock (clk2) is an ignore pin of the driving clock (clk1). Sinks of the driven clock are not considered sinks of the driving clock. This is the context...
  8. R

    Clock gating checks

    Actually there are some checks in STA like data to data checks, clock gating checks (so that clock will not come as a glitch on the Flip flop once it will get gated). for that we use AND/OR gate. but i am not able to properly understand the concept behind it. How should the enable pin of the...
  9. R

    [SOLVED] How do we set max fanout for clock nets

    I think that should be given in design constraints file known as SDC.
  10. R

    Clock Sinks while building clock tree during clock tree synthesis

    while building clock tree we need to provide clock tree defination: 1) clock endpoints 2) ignore pins In above diagram: clk2 is generated clock of clk1, so source pin of clk2 is ignore pin of clk1. but my question is what are the sink pins of clk1?
  11. R

    Reason of degaradation in timing violations after Clock tree synthesis

    i am working on 10nm technology.
  12. R

    Clock gating checks

    I am trying to understand clock gating checks concepts. But I am not able to understand it. Could anyone pls explain it.
  13. R

    Reason of degaradation in timing violations after Clock tree synthesis

    Utilization is only 60%. But yes, i have hot spots in some areas. While fixing the max trans & Max cap violations for clock cells while building the clock tree, would be the reason ?
  14. R

    High Transition time

    What if library not characterized upto 1000ps. I read in books, it will do extrapolation calculation, what is extrapolation calculation? and do we get corrupted timing report?
  15. R

    Reason of degaradation in timing violations after Clock tree synthesis

    CTS do DRC(DRC related to layout, eg: min width, min spacing violations) fixing also ?
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