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Clock Sinks while building clock tree during clock tree synthesis

riti

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while building clock tree we need to provide clock tree defination:

1) clock endpoints
2) ignore pins

1600432739505.png

In above diagram: clk2 is generated clock of clk1, so source pin of clk2 is ignore pin of clk1. but my question is what are the sink pins of clk1?
 

riti

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I don't follow. clk1 and clk2 are the same.
Source pins of clock trees in the fanout of another clock
For example, in Figure(which i have posted earlier) the source pin of the driven clock (clk2) is an ignore pin of the driving clock (clk1). Sinks of the driven clock are not considered sinks of the driving clock.

This is the context given in books.According to this, clk1 is driving clk and clk2 is driven clk.
 

ThisIsNotSam

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I still don't get it. Unless the clock is divided or muxed somehow, clk1 and clk2 are conceptually the same.
 

riti

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I still don't get it. Unless the clock is divided or muxed somehow, clk1 and clk2 are conceptually the same.
i got your point. But if we assume, clk1 is master clock and clk2 is generated clock. then sink pins for clk2 would be Flip flop shown in picture, but what would be the sink pin for master clock (clk1 in this case)?
 

riti

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the other flop on the bottom?
yes, but i forgot to mention that both upper flop and down flop are driven by clk2. Then, the clk divider (which we are assuming virtually for generating clk2) is the sink pin or not?
basically i am trying to clear my concept related to sink pin and ignore pins.
 

ThisIsNotSam

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what does it mean for a flop to be driven by a clk?

My head is spinning.
 

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