Source pins of clock trees in the fanout of another clockI don't follow. clk1 and clk2 are the same.
i got your point. But if we assume, clk1 is master clock and clk2 is generated clock. then sink pins for clk2 would be Flip flop shown in picture, but what would be the sink pin for master clock (clk1 in this case)?I still don't get it. Unless the clock is divided or muxed somehow, clk1 and clk2 are conceptually the same.
yes, but i forgot to mention that both upper flop and down flop are driven by clk2. Then, the clk divider (which we are assuming virtually for generating clk2) is the sink pin or not?the other flop on the bottom?