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Clock gating checks

riti

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I am trying to understand clock gating checks concepts. But I am not able to understand it.
Could anyone pls explain it.
 

KlausST

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Hi,

what about a little piece of context? A link to a document? Any information...

Usually you should not expect that response to your post is more detailed than your post.

Klaus
 

    riti

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riti

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Actually there are some checks in STA like data to data checks, clock gating checks (so that clock will not come as a glitch on the Flip flop once it will get gated). for that we use AND/OR gate. but i am not able to properly understand the concept behind it. How should the enable pin of the clock gate behaves to not to produce any glitch / and pass the clock gating check also?

I am refering this blog http://blogs.cuit.columbia.edu/zp2130/check_clock_gating/ for understanding it.
It is similar to concept given in book STA by J.bhaskar.
 

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