Reason of degaradation in timing violations after Clock tree synthesis

[riti]

In my block timing is looking fine till placement, after clock tree synthesis i am seeing huge degradation in setup timing. What could be the reason for that ?

when i have checked the placement of the flops among which timing is violated, it get changed compare to placement step.

Does tool fix DRC violations also (layout related) at CTS step? Or while fixing max trans , max cap violation at CTS step it degrades the timing. But again if tool tries to fix the max trans, max cap it should give improvement in setup timing.

what would be possible reason for degradation in timing at cts stage?

 

[oratie]

Possible reasons:
1) very high utilization (not enough empty space for CTS cells)
2) usually, the hold fixing starts at CTS stage - maybe you have too tight hold constraints (interclock holds?)

 

[riti]

Possible reasons:
1) very high utilization (not enough empty space for CTS cells)
2) usually, the hold fixing starts at CTS stage - maybe you have too tight hold constraints (interclock holds?)

CTS do DRC(DRC related to layout, eg: min width, min spacing violations) fixing also ?

 

[oratie]

CTS do DRC(DRC related to layout, eg: min width, min spacing violations) fixing also ?

It does for clock nets, only. But, I do not think it is the reason of degradation. Check the cell density map (local overutilization?)

 

[riti]

It does for clock nets, only. But, I do not think it is the reason of degradation. Check the cell density map (local overutilization?)

Utilization is only 60%. But yes, i have hot spots in some areas.
While fixing the max trans & Max cap violations for clock cells while building the clock tree, would be the reason ?

 

[oratie]

It is the possible reason, if the constraints are too tight.

 

[ThisIsNotSam]

Utilization is only 60%. But yes, i have hot spots in some areas.
While fixing the max trans & Max cap violations for clock cells while building the clock tree, would be the reason ?

depending on the technology, 60% is barely routable.

 

[riti]

depending on the technology, 60% is barely routable.

i am working on 10nm technology.

 

[ThisIsNotSam]

i am working on 10nm technology.

try reducing to 50%

 

[riti]

try reducing to 50%

i have worked on GPU blocks, where we have routed till 84% also.

 

[ThisIsNotSam]

i have worked on GPU blocks, where we have routed till 84% also.

still, try 50%. because the density is so low, depending on the design, localized hotspots become less likely. if it solves your problem, then you can try to increase density again and apply local fixes.