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Recent content by Renjith

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    stand alone Jtag programmer xilinx ISE

    You can download the Xilinx Lab Tools from Xilinx Website. This wont take huge space. This needs licensing, but you can always use it FREE during the evaluation period for 30 days. Rgds, Renjith
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    PLL design in Verilog language

    PLL design in Verilog hi Guys, Does anyone have the Verilog code for PLL? Thnx in adv, Renjith
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    Driving a Bidrectional Signal in Verilog Testbench

    Hi, How to write the verilog testbench to drive a value to a bidirectional port. Can someone suggest a simple example. assuming a module has a bidirectional bus, clk,enable, RW Thanks in advance Renjith
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    IR length info for non-xilinx devices?

    Hi All, How to get the info of the IR length for non-xilinx devices which are present in the xilinx jtag chain. i need to use chipscope for probing one of the xilinx fpga. hence i need the IR lengths of all the devices in the jtag chain(there are a couple of non-xilinx devices in the jtag...
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    FIR Design on XilinxSpartanII FPGA:Output Rounding Problem

    Developing Comblock Platform Com-1000 with Xilinx FPGA Hi, i have used com1008 and 1001 for some of our designs what is that u r looking at???
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    How to generate clock from FPGA to run another IC

    FPGA doesnot have any clock oscillators inside. So u need to use a Crystal oscillator for generating a master clock. FPGA has PLLs inside. so this master clock has to be fed to the FPGA to generate(using PLLS) other clock frequencies that has to be supplied to the different ICs on ur Board.
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    Floating point representation in HDL

    bitstoreal hi, if u need a synthesisable code for impelment a floating point addition, u have to implment the Floating point architecture using ur HDLs. floating point addition is quite simple, as it needs shifting and addition. we need to align the mantissas wrt the exponent, and then just...
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    help!!!!!!!!!!!implementation of FSM using PLD

    Hi Hemath, there are FSM modelling design entry tools which comes alongwith different FPGA vendor software IDEs. For Ex. if u r using Xilinx FPGA, Xilinx ISE software has got an integrated tool named "STATECAD". it's quite easy to implement ur FSM algos. they have the tutorials also for...
  9. R

    Protel DXP doesn't identify hardware connected to PC by JTAG

    Re: problem how do u know the hardware is not working when the fpga had been fused correctly? r u testing the status of some output pins for it?
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    Explanation of PLL functionality and related math

    what does pll do Therez lots of info on this Board itself. Search for "PLL" or Phase Lock in the Books upload/download or IEEE study papers.
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    Problem Xilinx system gen 8.1

    is the simulation of ur model using system generator working fine?
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    Problem Xilinx system gen 8.1

    What is ur RAM configuration of ur PC? if it's less, try to put an Extra Card, and then see the performance. To startoff, try out with some small functional model. Fo ex: a Counter design using System gen Block. Rgds, Renjith
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    req... design of DIRECT DIGITAL SYNTHESIZER

    Hi, Check out this link: h**p://www.xilinx.com/ipcenter/catalog/logicore/docs/dds.pdf This application note describes DDS IP core developed by xilinx.
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    How to make a full adder using half-adder module in VHDL?

    half-adder instantiation hi, using 2 halfadders u can implement a fulladder. connect 2 inputs to first halfadder, and connect the 3rd input and the "SUM" output of the first halfadder to the second halfadder. the "SUM" result of the 2nd halfadder will be a fulladder "Sum" output. Use an OR...
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    How to reduce clock speed in Spartan 2e FPGA?

    reducing clock speed Hi, hope u r trying to watch the output of the FlipFlops on the LEDs. ur eyes can't work that fast. try to c that in a scope or try to reduce the speed of ur Clk, so that u can see the toggling on the Leds itself. Use a 26 bit counter and give it's MSB bit to clock ur J&K...
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