FIR Design on XilinxSpartanII FPGA:Output Rounding Problem

[filmaker83]

rounding fpga

Hi guys! I'm an italian student. I use comblock
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Is there people, use and develope comblock?
Thanks ;-)
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for a communication system with a transmitter and receiver.
On My receiver, I use comblock board 3001 which is Dual-band 915 MHz / 2.4 GHz receiver, AGC, A/D converters

info here

Each Comblock has a xilinx fpga!

I would realize a filter in vhdl at output of comblock 3001.

Comblock 1008
is not efficient, so I would a vhdl filter and I would synthetize it on xilinx fpga com1000 for developing

Can you help me? I use ONEOVERT demo, but output there is not! Is there people use full version help me?

I would realize a fir low pass sampling frequence 40 mhz, elliptic filter, cut frequency 15 mhz and filter response is like an ideal low pass filter.

 

[filmaker83]

comblock code

I'm searching ONEOverT full version, can you help me? If there is anyone to help me i give him filter information to create a vhdl filter for me.
Thanks much!!!

 

[jawadshawa]

xilinx rounding

Its old problem ...and I had a version from Xilinx when I bought Xilinx Spartan 3E startekit ...

 

[filmaker83]

xilinx fir compiler rounding

And what was solution?

 

[filmaker83]

xilinx fir low pass

Is there people that used ONEoverT full version to create vhdl source code about filter?

 

[ali-mac]

xilinx fir compiler core output sign

Its old problem ...and I had a version from Xilinx when I bought Xilinx Spartan 3E startekit ...

Does Xilinx supply ONEoverT with the Spartan-3E starter kit? If so, where did you order it from?

Ali

 

[rsrinivas]

ONEOverT Full Version, VHDL Code about Filter

use matlab.
it gives u a better HDL code.
anyone need help can ask for further info.

 

[ali-mac]

Re: ONEOverT Full Version, VHDL Code about Filter

use matlab.
it gives u a better HDL code.
anyone need help can ask for further info.

Matlab costs a fortune. You have to buy the base module, then the filter toolbox and then the fixed point toolbox. It is way overpriced.

 

[filmaker83]

Developing Comblock com-1000

Thanks much ;-)

I use comblock

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Is there people, use and develope comblock?
Thanks ;-)
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[Renjith]

Developing Comblock Platform Com-1000 with Xilinx FPGA

Hi,
i have used com1008 and 1001 for some of our designs
what is that u r looking at???

 

[filmaker83]

Re: Developing Comblock Platform Com-1000 with Xilinx FPGA

Now i'm developing com-1000 board, i want to realize a FIR FILTER ad hoc. I'm using matlab for create a .coe file and xilinx ip core generator filter compiler v3.2 for implementing filter. I have write vhdl code for communicate with connectors J1,J2 etc, actmel micro controller and other componensts in the board, now i'm adding filter.xco created from core generator.

My problem is about I/O in the block of filter generated from IP core generator. I would the same bit lenght of the input, in output, for connections I/O.

In input i have DATA_IN [9 0] and instead DATA_OUT [30 0].
I would [9 0] for output!

FILTER is a FIR 21 TAPS with MAC, is there a solution for truncate bit?

Added after 5 hours 26 minutes:

I think, i can do a filter output rounding. Can i make it from 31 bits to 10 bits? Do I loss bits information?

 

[filmaker83]

Re: Developing Comblock Platform Com-1000 with Xilinx FPGA

I explain to you my STEPS:

:arrow:I use Filter Design Analysis FDA Matlab Toolboxes, for .coe file creation. When i set parameters filter quantization, i can decide to specify precision, output rounding, signed or unsigned coefficient etc etc.
I choose:
- 21 taps lowpass fir filter with window kaiser beta=0.5
- fs=40 mhz,
- fpass=10mhz
- coeff width 16 bits, signed, fixed point,
- datainput 10 bits, output 10bits with rounding convergence mode

:arrow: After I use ISE 9.2i - IP CORE GENERATOR Filter Compiler 3.2i for my XILINX XC2S200 SPARTAN II FAMILY
insert .coe file and set coefficient parameter, but there is not a solution, in the second step, i cant't select rounding output mode!
After matlab toolboxes settings, an other time, i must select sampling frequency, clock frequency and so on... is it normal?
The information i think is in the .coe file...isn't it? Instead i must insert the same parameters in filter compiler but not output rounding mode :-(

What is a solution? Can i truncate from 31 to 10 bit?

 

[filmaker83]

Re: FIR Design on XilinxSpartanII FPGA:Output Rounding Probl

I'm working for a thesis, is there a solution for my problem, please?

:arrow: Must I operate on the code, manually? What?
:arrow: Isn't an automatic option for filter output truncation (output rounding mode) for my spartan II xc2s200 ?

:arrow: Is there a block diagram which describes the MAC structure of filter and specify the code? for example, what is the structure which contains code block VCC, GND, FDCE, XORCY, MULT_AND, LUT4, etc.... block diagram connections?? (The code is generated from filter compiler code, in the datasheet there is generic mac structure!)