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Recent content by ramzitligue

  1. R

    multibuses affectation in vhdl

    Re: multibuses in vhdl hi, thanks for responding, and sorry because i don't mention that i already put all library and package.my problem is that my program didn't work when i simulated it on modelsim.
  2. R

    multibuses affectation in vhdl

    multibuses in vhdl hi,i want to do a multibuses affectation but it didn't work this is my program: TYPE data_port IS RECORD en : STD_LOGIC; write : STD_LOGIC; internal : STD_LOGIC; sel_dcache : STD_LOGIC...
  3. R

    forth processor - source code for arithmetics needed

    forth processor hi, i try to use forth processor and connect it to a memory,then i want to write a program which do arithmetic operations,write and read from memory but it's difficult to do.can anyone give me a source code and tell me how to transform it to .bin, because i searched but i don't...
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    request for VHDL source of arc processor

    arc processor hi, can anyone give me VHDL source of arc processor.thanks
  5. R

    xilinx/ise 11.1 dynamic power measure problem

    dynamic power hi,i want to measure the power which includes dynamic power.i use xilinx/ise 11.1.although i put the files that xpower needs in the same folder.but the dynamic power is always 0. i generate the "myfile.vcd" by isim using these commands but it seems that xpower doesn't care of this...
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    vcd add in modelsim - excampleneeded

    modelsim vcd hi, i try to use the command vcd add in modelsim but i don't know what the mean of object that i must add and use.can any one help by giving me an exeample.thanks
  7. R

    fpga - need explanation of different component consumption

    Re: fpga area hi, thanks for responding, but sorry i don't understand what is FF's and the advantage of their use in synchronous components and why they aren't used in Asynchronous components?thanks
  8. R

    fpga - need explanation of different component consumption

    fpga area hi, i made 2 types of components(written in VHDL): the first is Synchronous(use of clk) and the second is Asynchronous.the first one consumes less fpga area than the second.i think it's normal but i don't find the good explanation to this,can anyone help me?
  9. R

    can i use jbits with virtex 4? What are the other tools

    jbits hi, can i use jbits with virtex 4?if not what are the other tools that i can use to do the dynamic partial reconfiguration thanks
  10. R

    9.1i (XILINX) - problem with the area on FPGA

    Re: area on FPGA hi, where can find the option to desable the resource-sharing in ise9.1i?in order to make a comparison... Added after 17 minutes: thanks i found it
  11. R

    9.1i (XILINX) - problem with the area on FPGA

    area on FPGA hi, i built a component using VHDL,then i synthesize it and i found that the logic utilization on fpga was 1000 slices then i duplicate this component 4 times and i synthesize the new coponent and i found that the logic utilization on fpga was less than 4000 slices: it's 3500...
  12. R

    xpower brings me the same results with changed design

    power hi,i'd like to calculate the power consumed by my design so i used xpower but it usually brings me the same results although i changed the design i use the device xc4vlx100 and ise 9.1i.is there any problem with these platform?what can i do?can any one help me? thanks.
  13. R

    how can i calculate the bandwidth in network on chip

    Bandwidth hi, how can i calculate the bandwidth in network on chip
  14. R

    processor minimips lcd memory vhdl - can't see the content

    lcd memory vhdl Hi,i have implemented a processor minimips which is connected to memory on FPGA.the problem is that i can't see the content of the memory after write/read operation.can i use a module in vhdl which shows the content of the memory on LCD.please help me
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    vhdl - missing componentsafter synthesis

    Re: vhdl so we can't make a test on input en if it has the state 'Z'?if not haw can i replace it?
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