vhdl - missing componentsafter synthesis

[ramzitligue]

vhdl

hi, i wrote a program on vhdl :
entity b is
Port ( a0 :in STD_LOGIC_VECTOR (7 downto 0);
a1 : in STD_LOGIC;
s ut STD_LOGIC_VECTOR (7 downto 0));
end b;

architecture Behavioral of b is

begin
process(a1)
begin
if a1='1' then
s<=a0;
else
s<=(others=>'Z');
end if;
end process;

end Behavioral;


then i want to connect the output "s" of component b to to the input of another component b1 and here is the program of component b1:
entity b1 is
Port ( en :in STD_LOGIC_VECTOR (7 downto 0);
s1 ut STD_LOGIC_VECTOR (7 downto 0));
end b1;

architecture Behavioral of b1 is

begin
process(en)
begin
if en/="ZZZZZZZZ" then
s1<=en;
else
s1<=(others=>'Z');
end if;
end process;

end Behavioral;


the problem that after the synthesis i don't find the component b1 in rtl schematic.can you help me please?

 

[radix]

Re: vhdl

It's probably getting optimized away because it looks like what your code is implying is a wire.

If you rewrite the code for b1:

architecture Behavioral of b1 is 
begin 

process(en) 
begin 
  if en ="ZZZZZZZZ" then 
    s1<=(others=>'Z');   -- in this case s1 == en
  else 
    s1<=en;      -- in this case s1 == en also
  end if; 
end process; 

end Behavioral;

So it looks like s1 is always equal to en which means b1 can get replaced with
a wire.

Radix

 

[FvM]

vhdl

Apart from the shown redundancy, 'Z' isn't a defined input state, it's meaningful only for outputs.

 

[ramzitligue]

Re: vhdl

so we can't make a test on input en if it has the state 'Z'?if not haw can i replace it?

 

[radix]

Re: vhdl

Think about what you're asking. As FvM mentioned, 'Z' really only makes sense for an output. When you drive a 'Z' onto an output you are tri-stating that output.

What this means is that the output driver is shut off. It's no longer driving a 1 or 0, it's doing neither. The driver isn't sinking or sourcing any current. In an ideal case without a pull-up or pull-down resistor on the net and absolutely no leakage current, the last state driven onto that net will remain there indefinitely.

In the real world, tri-state cannot be sensed. A net is either a 1 or 0, or has some value between Vil an Vih which is really an unknown state. For input values within that range most receivers will either detect a 1 or a 0 but those values are meaningless.

Radix