9.1i (XILINX) - problem with the area on FPGA

[ramzitligue]

area on FPGA

hi,
i built a component using VHDL,then i synthesize it and i found that the logic
utilization on fpga was 1000 slices
then i duplicate this component 4 times and i synthesize the new coponent and i found that the logic utilization on fpga was less than 4000 slices: it's 3500 slices
is it normal?
i use ise 9.1i (XILINX)
can you help me?

 

[tinker_tim]

Re: area on FPGA

Its common for synthesis tools to optimize and share resources across entities or modules.
There are usually options to enable resource-sharing, as well as flattening -hierarchy, etc.

If you disable these features, then you will be able to get your 4000 slices, though you
probably don't want to do that in the long run.

Hope this helps.

Tink!

 

[ramzitligue]

Re: area on FPGA

hi,
where can find the option to desable the resource-sharing in ise9.1i?in order to make a comparison...

Added after 17 minutes:

thanks i found it