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Recent content by rajavel.rv

  1. R

    Need Model file for BJT for Tanner Tool v13

    Need Model file for BJT Tanner Tool v13 Hi all, we are need a BJT Model file 250nm, for Tanner tool v13. (urgent),.. anybody have the model file, please help us,.
  2. R

    VGA interface using DB15 connector in VHDL

    Yes, but our board not having the DAC in between FPGA to VGA connector, they are directly connected 5 signals(hsync, vsync, r, g, b) to FPGA, how can am given the data as BYTE to BIT,.
  3. R

    How to Synthesize File handling VHDL code in xilinx

    Thanks guys, am using memory to load the data, now its working.,, Thanks & Regards Rajavel Ashokraj
  4. R

    VGA interface using DB15 connector in VHDL

    Hi Guys, we are having a doubt to interface with VGA using DB15 connector it having the input and output pins of hsync, vsync, red, green, blue, all will be single bit,. we are given hsync and vsync properlly, but the problem is how can we are given data to this device, because we are...
  5. R

    How to Synthesize File handling VHDL code in xilinx

    Hi guys, am writing a vhdl code with file reading and writing (image), how can am synthesize this code, in xilinx software, where the image file will be added, pls help as soon as possible,.. Thanks & Regrds, Rajavel Ashokraj
  6. R

    how to Compile and simulate .vp file

    I have a .vp protected file [Model]which is generated by cadence. But i want to simulate this file in synopsys vcs tool. Please help me on this, what are all the commands use to compile and simulate.
  7. R

    System verilog file reading and writing

    Thanks mr-flibble, seriously i don't know this.. your are really helped me..
  8. R

    System verilog file reading and writing

    Hi all, Please share any sample code for text file reading and writing in system verilog for test bench.
  9. R

    ROHC CRC Calculation

    Hi ads-ee, Thanks to send this link, its very useful for me. Thanks & Regards, Rajavel Ashokraj
  10. R

    ROHC CRC Calculation

    Hi all, I have a polynomial equation of CRC(cyclic redundancy check) for ROHC compression and decompression technique, the polynomial equation equation is shown below, CRC 3-BIT : C(x) = 1 + x + x^3 CRC 7-BIT : C(x) = 1 + x + x^2 + x^3 + x^6 + x^7 CRC 8-BIT : C(x) = 1 + x + x^2 +...
  11. R

    C: is Access Denied having full control production problem in administrator

    Hi, am plan to product my c:/ for my user accounts, so read the procedure in internet and followed this step is shown below, 1. right click the c:/ then select the properties and security option 2. Select the users 3. Edit the Permission of users Then am select Full control of the users...
  12. R

    Simulating VHDL code with R-L load

    if its possible to do this in verilog hdl; if its possible means how can i design this type of analog hardware in verilog code and please post which book material or link was good reference for me. ref : **broken link removed** regards rajavel.rv
  13. R

    Verilog Tasks and Functions vs Modules

    refer this link : https://www.lsi.upc.edu/~jordicf/Teaching/secretsofhardware/VerilogIntroduction_Nyasulu.pdf regards rajavel.rv
  14. R

    xilinx verilog code for 512 point fft processor

    Hema, refer the below link its helpful for u to write a verilog coding and block diagram for 512 point fft processor; link : **broken link removed** regards rajavel.rv
  15. R

    fpga schematic difference

    Hi anybody know what is the difference between schematic and path schematic using fpga design... regards, rajavel.rv
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