Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to Compile and simulate .vp file

Status
Not open for further replies.
R

rajavel.rv

Member level 3
Joined
Dec 1, 2010
Messages
66
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,288
Location
Pondichéry, Puducherry, India, India
Activity points
1,685
I have a .vp protected file [Model]which is generated by cadence. But i want to simulate this file in synopsys vcs tool.

Please help me on this, what are all the commands use to compile and simulate.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top