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If i have IO pads related to SPI protocol..are we saying i should enquire about the other side of the IO pads and accordingly proceed with timing constraints?
Disclaimer - havent done this before - so i really dont know how to go about this. We do have vendor constraints but i really want to be...
Does anyone know SPI timing constraints that comes from vendor - does that support all CPOL CPHA based 4 modes?
We heard back from vendor it does, but i am not sure how that works out. We plan to run ext clock at 62.5 mhz, ext refclk is 250 mhz, apb / pclk is 125 mhz.
Any help is much appreciated!
Is it necessary to have sequential optimization turned on in synthesis to pass LEC? Or its just runtime tradeoff?
1707856856
Also , is it possible to run LEC on RTL with empty modules that we delete in back end?
Incoming RTL has empty modules for god knows why - and i delete those in my back...
Dumb question, why do we need to extend the well at all? If each std cell has the well inside it wont we get continuous well by abutment? I see these cells too and would like to finally know what endcap cells are doing. Seeing them on core boundary, surrounding macros..
My run has determined 25k module pairs for a large hierarchical design. So it is running painfully slow - been 2 days with only ~7k modules processed!
I already have no translate for lower level hierarchical PNR blocks and srams turned on, so i am not sure what else do i need to add to speed...
The IO pads shows 12-15 pins and some of them are bi-directional. Do you need anything special while writing timing constraints on IO pads?
If someone has done this before, any guidance is appreciated. Right now there's enough reg2reg crap so i have IO timing false pathed.
In physically designing a floorplan and doing place and route - how do you deal with 2 instances of the same module?
Case A : same instance stamped twice into the floorplan?
Case B: both flat as sea of gates in the floorplan (not hierarchically implemented and stamped)
Q. What happens if...
If you need to isolate certain standard cells separate from other cells in the design, we will need to cut standard cell rows around these cells? Then draw a ring in OD (oxide diffusion), NW, PW layers?
will that suffice? These layers OD, PW and NW need to be tied off to power nets..Will this work?
Well my rationale for following this is intuitive:
Setup, hold, noise are all based on timing windows. So you fix all clock cap, trans violations first. Then you want realistic violations, so you need to fix max cap and max trans on data path. This ensures that you see realistic numbers...
No, this is sure to become an endless runaway loop.
If you cannot step back to place and route, then this is the sequence i have followed before.
clock max cap, trans (lock the clocks down asap)
Then data max cap/ max trans
Then look at remaining setup violations. For the rest, this is helpful...
Agree with thisisnotsam's response. Another case is when you need to do your own DFT for that IP. Most cases the IP will come with its own ports and documentation on how to test it, but if you need any additional testing or anything slightly more complicated on that front, you are free to add...
But in any design you need to at least find the breaking point as your due diligence. Start wherever, but build up to find where you start seeing shorts increase, timing crap out, runtimes explode. All part of knowing the design, this should be true regardless of tech node.
Hi,
I am wondering how to write these generated clock constraints at clk out pin, when there is a clk in coming in, div_en and cg en are other signals going to flop and clock gate respectively.
Can i just say
create_generated_clock -source <CLK pin of flop in the picture> -master CLKIN...
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