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Recent content by qual_ti

  1. Q

    metal filling and it's impact on timing.

    Thanks for all who helped in this discussion. My concern is , how the metal fills effect the coupling cap ? Does the metal fills connected to either Power or ground. I thought these are floating . How steady state state signal increase or decrease the coupling cap? or only switching nets can...
  2. Q

    Library Characterzation

    Hi, How the cell libraries are prepared.
  3. Q

    what are minimum pulse width vioaltions.

    Hi All, What are min pulse width violations ... How to get tehm in PT and how to fix them.... thanks in advance...
  4. Q

    How skew value and max insertion delays are calculated?

    Re: clock skew and timing thanks for reply. My question is we set these skew and insertion delay values in CTS specification file... On what basis these two values decided ? One more question ... Which one is important either Global or local skew ? and why ?
  5. Q

    What are the concerns while doing power planning in spacing between stripes ?

    what are the concerns while doing power planning in spacing between stripes ?.... thanks in advance....
  6. Q

    How skew value and max insertion delays are calculated?

    hi, why skew should be minimal? How skew value and max insertion delays are calculated which we can specify in the CTS specification file ?
  7. Q

    what is IR -Drop Analysis and documentation....

    Hi ASICers, Could I get scratch to cream information on IR-Drop. Is there any good pdf ,ppts and links regarding that. What r the major challenges in recent technologies etc. Please start from scratch... Thanks in advance... Regards Qaul_ti
  8. Q

    what is min pulse width check and how to fix those violations.....

    what is min pulse width check and how to fix those violations..... what are other considerations while fixing those violations. I need from scratch.... pls provide this info....
  9. Q

    metal filling and it's impact on timing.

    hi see this paragraph... " Using a signoff quality metal density which adheres to the rule deck of foundry for metal filling at every stage of routing ensures that we get a signoff quality metal fill and avoids any surprises down the flow. When metal fill is done in a design it could as well...
  10. Q

    metal filling and it's impact on timing.

    thanks for info. How these meal fills impact on timing and cross talk. thanks in advance qual_ti
  11. Q

    metal filling and it's impact on timing.

    Hi, Why metal filling is done in ASIC design flow ? If metal fill done, how it impacts the timing and cross talk. Please share information regarding this. Thanks in advance qual_ti
  12. Q

    half cycle paths violaations in STA

    thanks a lot kbulusu.............
  13. Q

    How to write timing constraints

    very good info...............
  14. Q

    Is Clock duty cycle should be 50% ?

    Hi, Thanks for info on 50% duty cycle. ON what basis the minimum pulse width of the clock is decided??????????????? and if duty cycle is less than 50%(ON period of clock ) then any impact on power (both dynamic and static power) ?????????? Thanks in advance qual_ti
  15. Q

    half cycle paths violaations in STA

    Hi Kbulusu, Thanks for ur quick reply. This path is reg to reg path only. It is not clock_gating group also. It is after route opt stage. I am seeing this type of violation in STA report. I have to fix this violation. Can we ignore the these half cycle path violations ? If we ignore what r...
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