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The cell's schematics and layout will be created in a tool such as Cadence Virtuoso. This gives you GDS, spice and LEF views.
To create the .libs, you run a library characterisation tool, such as Encounter Library Characterizer. This will simulate the cells in spice and then build .libs from the results.
I guess that you means ASIC cell library for synthesis and APR.
The above said that cell libraries is created by layout tool such as Cadence Virtuoso.
But as a digital circuit designer, we use already-made cell library developed by foundry.
Typical foundries are like TSMC, UMC and so on.
They will provide you with corresponding cell libraries and model for your ASIC development.
To access such libraries, ask your teacher if you are a student or ask your company if you are a engineer.
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