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First know the number of sink pins i mean register/Flops in the design. If they are 1000 for instance, and let say 20 is the fanout for a buffer. To drive 1000 flops you need atleast now 1000/20 (50) buffers, and you need 3 buffers to drive this 50 buffers.
So, you need 50 buffers at the 3rd...
If the reset signal has a large load, i.e.., if the fanout is more, than there could be a timing vioaltion and also design rule violation like maximum constraint. To fix this one can do high fanout synthesis (HFN's) the same way as clock tree synthesis is done.
In the clock tree specification...
Voltage Storm
voltage storm reports the ir drop at all nodes in ur design
This log tells you that those many nodes are falling with in that range.
You can always cahnge the threshold and look how the power grid changes its colors.
astro transition time
while doing timing analysis you have option in the form where in one can optimize drvs especially. enable that switch. May be that can fix the problem to an extent.
Instance and cell
Cells are none other than the normal cells as nand, nor etc..,
Even instances are same as cells. But in the tool perspective we can have many instances of the same cell.
This is usually because if the same cell name (eg:nand) is used many times in the design, and later u want...
Floorplan
Block halos are required because we dont want any standard cells to be placed around the blocks. If they are placed then the router would face difficulty to connect the block pins to any other cells. As router is blocked by these standard cells.
Added after 3 minutes:
One should...
As per my knowledge we do clock tree buffering to balance all the clock paths and reduce the skew even. This is to check if the clock is reaching all the sync pins at the same time or with in the limits.
we also insert buffers mostly in the data path to avoid hold violations to increase the...
Re: IC Design Interview
i want to share some thing about how the temperature can affect the delays....
At lower temperatures the atomic sites of the material (what ever it is) would stay where ever they are. so an electron would see an vaccant area between the atomic sites and traverse freely...
Hi,
Hold is more important bcoz if there is any setup voilatin one can avoid it by decreasing the frequency of operation. since hold is independent of frequency of operatiin u need to resolve the problem before implimenting the design on the silicon.
HFN synthesis is done for the reset pins etc.., before the CTS. This is done during the Zero rc stage while the clock nets are synthesized only during CTS. Because the clock nets are to be laid with extra care.
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