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Recent content by pramodm

  1. P

    transferring from clock domain

    i am not sure a single clock source will generate 2 clocks with same frequency with unknown phase relationship. even such source is there use only one clock from that source for both the blocks that are exchanging data, instead of synchronizing the data paths between the blocks. In general for...
  2. P

    transferring from clock domain

    I did not clerly understand following statements "two clocks name Clk1 and Clk2 from the same clock source and the frequencies of both the clocks being same" "the clock is send to different designs" i think, No need of a synchronization circuit between the paths of two designs. If same...
  3. P

    Wireless notice board help

    real time applications of wireless notice board hi, I am also doing same project Can u please provide the documents(Schimatic and code ) with you, with or with out GSM module. thanx
  4. P

    IEEE paper required- Creating a PowerPC Subsystem Plus User

    IEEE paper required An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic thanx
  5. P

    Looking for driver code for 1394

    Re: firewire please provide specifications for me thanx
  6. P

    Looking for materials on USB 2.0 EHCI host stack

    Re: USB 2.0 EHCI host stack please can you provide linux USB stack for me
  7. P

    implementation pipeline cpu with verilog

    pipeline verilog for a simple pipeline cpu design u can refer any HDL(verilog) book verilog hardware description language by moorby has a simple example on processor design
  8. P

    Starting IP company-what does a company need to get started?

    Starting IP company its good idea first you create catlog of IP publish it you can get some clients
  9. P

    Best book to learn Verilog?

    best books to learn verilog verilog hardware description language by moorby is good one
  10. P

    Clock Tree Synthesis topics and guide

    Clock Tree Synthesis primetime user guide may help you
  11. P

    Questions about sensitivity list in Verilog and what type of language is Verilog

    verilog questions reading of any HDL book will clarify your questions
  12. P

    how to reduce total hormonic distortion in sin waves?

    %THD reduction use low pass filter
  13. P

    Regarding Skew and frequency/Clear me

    hi your first statement is correct, with postive skew, there is more time to the signal to reach the destination for setup slack analysis so the time period decreases. but it may violate hold slack and the skew effect very little on frequency of operation.

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