Guidelines for RTL and Behavioural

[ankit12345]

I need guidelines for RTL and behavioural............
IN VERILOG

What Verilog constructs are NOT allowed in RTL????
Why???

Can i use "+" for addition in RTL???????

 

[arp]

See any book related to verilog, they mention some verilog behavioral programming like fork and join which are not used in RTL.

Yes you can use + in the RTL
For converting to gate level, the converter tools will use the best logic for ur code
for example if u want to add a bit to the two bit number the tools uses the simple adder.

 

[subramanyam]

go through the site,

**broken link removed**


subbu.

 

[rakesh_aadhimoolam]

hi

 

[elec_student]

Hi,

Good coding guidelines

 

[aji_vlsi]

I need guidelines for RTL and behavioural............
IN VERILOG

What Verilog constructs are NOT allowed in RTL????
Why???

Can i use "+" for addition in RTL???????

There is infact an IEEE standard for Synthesisable subset in verilog. I highly recommend use of Design checker such as Leda/SpyGlass to detect suc issues early on in the phase (tahn going till synthesis and finding it out)

Regards
Ajeetha, CVC

 

[shiv_emf]

linting tool provided by cadence ..
"Hal" is command for checking synthesiable code...
it gives various errors on various aspects .. nice tool for writing synthesiable code ..

 

[matthew_wang]

RTL and behavioral coding is from different design view. The latter focuses on module, it does not concern the internal details.

 

[amitgvlsijune06]

RTL level :
1. Essentially synthesizable
2. Based on register transfer level design helpful in pipelining and parallelism of architecture.
3. in simple terms uses only the synthesizable constructs of verilog/vhdl

Behavior level:
1. Can be both synthesizable/nonsynthesizable
2. Not necessarily a register based transaction
3. used mostly for test benches specifically self checking testbenches for simulation purpose.

 

[darylz]

http://www.cs.ualberta.ca/~amaral/courses/329/labs/VHDL_Guideline.html
http://www.eda.org/rassp/vhdl/guidelines/guidelines.html
http://doi.ieeecomputersociety.org/10.1109/DAC.1996.149

 

[bigrice911]

nLint is a not bad tool for you.

 

[sakshi gupta]

Can anyone please tell me about the list of RTL checks that should be checked by formal engine ?

 

[pramodm]

look this one

 

[ljxpjpjljx]

furthermore,some coding style is not supported in synthesis!

 

[vid31]

Hi,

What is Spyglass?

And would anyone brief me about it's use?

And is it synopsys or cadence tool?

Regards,
Vid31

 

[sathi.repala]

Go through this document, i hope it will help you...

 

[vid31]

Hi,

Can any one help me with spyglass?
I am using the library in VHDL file and same I have specified in command line for spyglass.
But in the reports it is saying that Missing logical to Physical mapping for that library.

So, does any one have faced this kind of problem?

regards,
Vid31