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Recent content by pradeep2323

  1. P

    How to generate a clock using a 1Hz clock in Verilog?

    Re: CLOCK GENERATION you can get it in google. or try in search engines. I know the paper which will provide you complete details regarding clock dividers and pll "clock divider made easy" topic search in google and you will get the link for download
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    Interview question about a FIFO depth

    Re: fifo depth question no need of fifo, but if u want to support for worst case scenario also then it should be 25
  3. P

    What are the advantages of AHB over AXI bus protocol ?

    Re: AHB V AXI Hi Carrot, I think split-retry transfers are there to increase or maximise the utilisation of bus bandwidth efficiently. Is there any other advantages P
  4. P

    What are the advantages of AHB over AXI bus protocol ?

    Hi Guys, Could you please tell me what are the advantages of AHB over AXI bus protocol and viceversa
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    10bit LFSR design - request for resources

    10bit LFSR design Hi , I need to design a random number generator for my project. Please anybody share the any code regarding this 10bit LFSR. Thanks, PSS
  6. P

    SYSTEM VERILOG VERIFICATION ENVIRONMENT

    Hi, Thank you for your reply.Presentely we are working on modelsim 6.2 version. will it suitable for verification. Regards, Pradeep
  7. P

    SYSTEM VERILOG VERIFICATION ENVIRONMENT

    developing verification environment in verilog Hi, I have to develop a system verilog verification environment for my project. could u plz help me out in this regards,and also provide some tool knowledge and reffer some website form which i can download some materials. regards, Pradeep
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    What are the functions of PRF64?

    Hi guys, Can anybody tell me about PRF64 function. I know that we are using this to generate psuedo random numbers. Please put more information regrding this....... Regards, PPPPPP
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    FIFO depth calculation

    fifo question 80/100 8/10 Hi, One of the most common questions in interviews is how to calculate the depth of a FIFO. Fifo is used as buffering element or queueing element in the system, which is by common sense is required only when you slow at reading than the write operation. So size of...
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    Assigning value to a inout bit

    Hi, How to assign value to a inout bit in a test bench. I want to assign a value to a inout bit of design in testbench at perticular time. Could you please tell me the ways...... Regards, P
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    DEPTH OF A SYNCHRONOUS FIFO

    Hi, How to calculate the depth of synchronous fifo. In where we should use it?
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    How to design a counter by deriving clock?

    hi, if our design works on some X MHz. then how to design a counter by deriving that clock?
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    regarding cycle based symulators and event based symulators

    Re: regarding cycle based symulators and event based symulat hi malligaru, cycle based simulators are usefule for synchronous designs where operations happen only at active clock edges works on cycle by cycle basis.timing information between two clock edges is lost. significant performance...
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    Looking for information about multicycle path

    can anybody tell more regarding multicycle path?
  15. P

    How to know that our setup and hold time are violated?

    how can we come to know that our setup time or hold time violated???
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