How to know that our setup and hold time are violated?

[pradeep2323]

how can we come to know that our setup time or hold time violated???

 

[xstal]

Re: setup and hold time

seeing the timing report which is generated by the tool

 

[rjainv]

setup and hold time

Constrain your design ( e.g. create clocks on all external/internal clock sources) and look at timing reports...

 

[yjkwon57]

Re: setup and hold time

you can identify the setup- and hold-time violations in both static and dynamic timing analysis.

 

[shiv_emf]

setup and hold time

at what stage of design u r checking?

 

[thamarai]

setup and hold time

u can generate reports for timing violations

 

[quan228228]

Re: setup and hold time

Both in FPGA and ASIC, you can read the timing report, if the path slack is plus, then the setup is met.