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Jayanth, I am looking something that a BT module(Hardware) that can be soldered on the PCB with USB D+ and D- features or pin's so that it can interface with the microcontroller with traces. I do not require a USB connector fixed to that.
Hi , could any one suggest Class2 Bluetooth module that has USB compatibilty to interface with the microcontroller. Meaning the Bluetooth module should have D+ and D- so that it could interfaced to the microcontroller.
regards
Phutanesv
hai friends,
Can anyone tell what is meant my blockage.
We have terms like standard cell blockage, placement blockage and macro blockage and routing blockage
what does it mean. Is that meaning if i put blockage only standard cell will be placed and macro will be placed and routing will be...
Re: Design rule question
may be because metal may carry more current . where as poly will carry less
current. since matal carry more curent there is a chance of cross talk issues
so the spacing between metal to metal is large compare to poly spacing
manfacuturing grid is like
we will be having grid in the tool . we have a start with a paritcular gird and to proceed our design flow, so that the compnent or cell which we are to place or assemble will be alingned in a proper way so that during manfacture it will be quite easier to fab...
Re: MACRO BLOCKAGE
hai dude,
Advantage is macro are the most power hungers.
not only the area (area here is for routing purpose we get more area so no congestion) u r saving power too. IR drop will be less,
capacitance will be less becos of interconnect wire lenght is less.
how to solve negative slack
Nothing confusion
set up or hold violation occurs depending on the value we get
That is for SET UP= RT-AT and Hold is AT-RT
we should always have a positive value.
just c to get a negative value in set up AT must be more
similarly for Hold RT must be more.
but...
negative slack time
hai dude,
Hope u know what is slack . it is diffrence between requried time and Arrival time.
Slack =RT-AT =set up
slack = AT-RT = hold
If RT is greater than AT leads tp setup
If AT is greater than RT leads to Hold.
Means slack or setup occurs of the signal reaches...
Re: Clock Tree Synthesis
Hai,
hope u know what is CTS.
Its just playing wit the inverters or buffers or dealy cells such that making all the flops in reaching the clock at same time.
Well regarding expertise, just managining to slove the issues and considering why is that issue coming into...
hello dudes,
Where do we check set up and hold violations.
like on which clock pulse 1 0r 2.
if not understandable,
do we check setup on clock 2 or on clock 1
pls let me get expalined
Dear dude,
U have said as X any Y are giving their uotputs and 1 and 0 depaending on their
corrosponding inputs.
But my question is what is your requrinment.
1) with those output do u need to which gate to construct
2) or which gate is X and Y
regards
Phutane
Dear Dudes,
I need a small clearance.
Generally there are two skews positive and negative.
Also a equation is
T+Tskew= Tc2q+Tcombo+Tsetup
So if i get a postive skew my time period comes down hence frequency increases
Since T= Tc2q+Tcombo+Tsetup-Tskew
similarly if i get nagative skew my...
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