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Recent content by pawangupta

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    Configurable case loop in verilog

    Hi all, I want to write a configurable verilog code of case statement....please help me, if any idea... Example_1: In this simple example, i know how many case expressions may exist in my case loop...4: parameter COUNT_WIDTH = 4 case (COUNT_WIDTH) 4'b0001: something; 4'b0010...
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    stoping AXI Write requests

    Hi ljxpjpjljx, Can you please elaborate it. Thanks Pawan.
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    stoping AXI Write requests

    Hi All, Suppose a Bus master (Processor) request continuous write transfers to an AXI slave, & i am having limited memory to store those write data & because of my hardware processing delay, memory are not instantly vacated. Is it possible to stop the Bus master to initiate further...
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    latency & throughput

    Hi all, What does mean by Throughput & Latency of a System or Bus? How these 2 are different. Suppose i had designed a DMA Controller / AXI Bus interface, please explain me how to calculate throughput & latency of DMAC/AXI? Thanks
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    AXI throughput & latency

    Hi all, I had designed AXI Master & Slave interface....For which i want to know the followings: What is meant by AXI bus throughput? From which point to which point it is measured? How to calculate it? What is meant by AXI bus latency? How to calculate it? Please help me on this...
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    Where to use AXI, AHB & PLB bus interface in SoC ?

    Re: Axi/ahb/plb Hi rca, Can u please elaborate 1st point. Thanks Pawan
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    applications of AXI-AHB

    Hi, Thanks rakko, this is clear to me now if i am going to burn my DUT with AXI bus interface into Xilinx Virtex 5 FPGA....i think so this board supports PLB bus...not axi...for this i had designed PLB bus interface. From where can i get related documents/info...on which board which Bus...
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    Where to use AXI, AHB & PLB bus interface in SoC ?

    Hi all, Can you please tell me: 1. If someone asks what is the max operating freq of AXI, AHB you had designed? What should be the answer (in interview)? 2. Where to use AXI, AHB & PLB bus interface in Soc? Thanks Pawan.
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    applications of AXI-AHB

    Hi all, Can you please tell me; Where to use AXI bus, where AHB bus, as both are high frequency interfaces by AMBA...? Thanks
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    physical synthesis timing error

    Hi all, I had done logical synthesis using SYnplify Premier & PAR with ISE..All timing constraints were meeting while after logic synthesis doing physical synthesis is giving timing error (-ve slack)....how it could happen...Can anybody explain it...
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    Help me generate a hierarchical netlist using Synplify Premier and Xilinx ISE

    Re: netlist hierarchy Thanks Rakko, its working....i was aware of this attribute which can be added in .v files...but was not confident....u makes my thing easy...Can't we do in my script file alone..instead of going to each .v file..?
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    Help me generate a hierarchical netlist using Synplify Premier and Xilinx ISE

    Hi all , I want to generate hierarchical netlist using Synplify Premier & Xilinx Tool: Synthesis using Synplify Premier, PAR using XIlinx ISE. Written a tcl script separately for Synplify Synthesis & one for Xilinx PAR. I had called Xilinx PAR script into Synplify Synthesis script...
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    io delays in synplify premier

    Hi randyest, Thanks for the link & your reply... I know my design in FPGA works on 2 clocks derived by DCM in my FPGA. You had given more possibilities: Case 1: If Chip 1 & 2 works on different clock other than my FPGA.... Case 2: Chip 1 & 2 clock same as my FPGA... Whether as an IP...
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    io delays in synplify premier

    Hi, Say for example, my design in FPGA is running at 100 MHz feq (period =10ns). My design top is having AXI related inputs & outputs which should work on pro clock. Definitely my chip has to be connected to outside chip on a board. Plz go though attached diagram... Case: I am not...
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    io delays in synplify premier

    Thanks randyest....I will go through the attached link...if still not clear to me i will get back to you...
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