Help me generate a hierarchical netlist using Synplify Premier and Xilinx ISE

[pawangupta]

Hi all ,

I want to generate hierarchical netlist using Synplify Premier & Xilinx Tool:

Synthesis using Synplify Premier, PAR using XIlinx ISE.

Written a tcl script separately for Synplify Synthesis & one for Xilinx PAR. I had called Xilinx PAR script into Synplify Synthesis script using xtclsh...I am trying to generate hierarchical (Post MAP, Post PAR) netlist using "define_global_attribute syn_netlist_hierarchy" in .SDC script file....also adding "define_global_attribute xc_use_keep_hierarchy". But after PAR in batch mode netlist generated are flattened netlist only....I want to know the issue in any way...

Please let me know the point where i am lagging.....

Thanks

 

[rakko]

Re: netlist hierarchy

Give this a try, it works in synplify.
Add the "syn_hier" attribute to the module declaration:
module_name (ports) /*synthesis syn_hier="hard"*/;

Attach the "KEEP_HIERARCHY" property to the instantiation of the module:
module_name instance_name(port_mapping) /*synthesis xc_props="KEEP_HIERARCHY=TRUE"*/;

 

[pawangupta]

Re: netlist hierarchy

Thanks Rakko,

its working....i was aware of this attribute which can be added in .v files...but was not confident....u makes my thing easy...Can't we do in my script file alone..instead of going to each .v file..?