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Recent content by pavi622

  1. P

    what are un classified vt cells?

    What are unclassified vt cells
  2. P

    STA & PD inter relation

    hi i have some doubts, can any1 plz clarify 1. What is the difference btw RTL & synthesised netlist 2. What are PVT corners & how are thy defined. 3. What is the relationship between PVT corners & delay for a particular library?
  3. P

    Defining Operating Conditions in PD using SoC Encounter

    am aware of that timing operating conditions. Apart form that if i want to define any other operating condition. how to go about it ---------- Post added at 17:23 ---------- Previous post was at 17:23 ---------- am aware of that timing operating conditions. Apart form that if i want to define...
  4. P

    Defining Operating Conditions in PD using SoC Encounter

    I am using SoC encounter for project. i wan to introduce operating conditions into the flow. I want to know, 1. How these operating conditions are defined? 2. Is it dependent on synthesis & RTL? 3. On what basis these operating conditions are decided Also . what is the difference between prePD...
  5. P

    clock gate cloning using SoC encounter

    thank you, i have some more doubts, 1. what is the difference between prePD and postPD netlist? 2. how does total power & power density differ wrt PD?
  6. P

    clock gate cloning using SoC encounter

    on what basis a PD engineer will decide whether clock gating must be done or not?
  7. P

    relation between CTS & design

    How CTS specification file be written or modified with respect to design? How design & CTS strategy adopted are interrelated?
  8. P

    grouping instances in SoC encounter

    the thing is the design contain some memory, but memory complier is not available for hardening the memory. While optimising the rest of the logic, the memory which is realised as flops are also optimised. Reason is SoC encounter see these flops as just instances/standard cell. As a result...
  9. P

    grouping instances in SoC encounter

    Hi, I am working on a design, where i dont want to optimise a group of instances. How can i go about doing this using SoC encounter
  10. P

    clock gate cloning using SoC encounter

    If some one could tell the brief flow, that would be more helpful
  11. P

    clock gate cloning using SoC encounter

    hi, what is clock cloning? How it can be implemented using SoC encounter? Can any one plz help.
  12. P

    reg t output setup fixing

    How to know whether the buffers inserted are unnecessary or not and do not affect other paths?
  13. P

    reg t output setup fixing

    Hi, i am working with SoC encounter for PD. For a particular design after PD, when verified for timing am getting to many reg to output setup violations. I cant upsize the cells as the cells used are of maximum drive stregnth. So is it some how possible so that i can controle the PD...
  14. P

    Low power design using SoC encounter

    Hi , I am doing Flat implementation of IPs using SoC encounter. If i want to integrate low power design along with the flat implementation how to go about it? What does CPF mean? What does it contain? How to crate power domains & on wat basis we create power domains?
  15. P

    Buffer tree synthesis

    Thanx, But can any of the signal net be buffered similar to clock? If do so are we restricting the tool in its optimization?
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