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I am having design which requires tristates (for blocking) in certain conditions.i am getting fault coverage of 93.48(%) for my design by using Tetramax ATPG tool.
Tristates were properly driven with single instances.I heard that the asynchronous pins of tristates are not properly...
hai this is pavan M.tech in vlsi having work experience on vlsi testing projects.I need help regarding phd admission in u.s.a. i have masters degree. i need to take gre/tofel for admission.How to approach top university professors in my domain .
Re: how to make following code with high impedance synthesiz
yes they are replaced by pull ups by xilinx synthesis tool . now what should i modify code so that it can be executed in synopsys design compiler
Added after 5 minutes:
In my architecture when internal blocks gets blocked . Then i...
Re: how to make following code with high impedance synthesiz
i am able to synthesize it in xilinx ise simulator . But unable to do in synopsys design compiler ..
Tell me clearly what modifications i should make. Regarding s1 and s2 they are stage index and they change...
hi freinds , i am having problem regarding high -Z in my design .My design is not able to be synthesized in design compiler . In my design i need to block some ports for some condition .my raw code is like below .The situation is when some port is in Z impedance some operation should be done (in...
hi freinds , i am having problem regarding high -Z in my design .My design is not able to be synthesized in design compiler . In my design i need to block some ports for some condition .my raw code is like below .The situation is when some port is in Z impedance some operation should be done...
Re: Regarding how to make tristate based designs synthesizab
if(s1='Z' and s2='0') like this so many conditional statements using Z were there in my program .......
I controlled Z by using enable when it is output node but internally should i use signals to control ...
lattice internal tristate
Hi everbody,
I am having design(vhdl) for banyan switch in which there is condition that some ports should be blocked in certain situation.. so,"It is compulsory that i should use tristates in my design"...
first use design compiler for synthesis there u specify scan style as mux and then read netlist (synthesized) into tetramax .....
I have done my thesis work using tetramax for my dft based design.. may i know to which college u belong to....................
tetramax manual
hello freinds i am using two commands two open tmax
csh , source /home/student1/synopsys/synopsys.cshrc , tmaxgui ........ after that tool is opening . I have done dc(dft compiler flow ) to my design and generated corresponding design.ddc, .spf(stil file)...
add clocks tetramax
hello freind , i have seen your reply. i have tried commands what u have send but no change
in response............
My problem is that i have an rtl design (behavioural) in "vhdl" of banyan switch. The
architecture needs scan cells to be...
tetramax .lib
read netlist banyan.vhd
BUILD> read netlist banyan.spf
BUILD>
BUILD> run build_model banyan
BUILD> run drc banyan.spf
BUILD> drc
BUILD> drc
i am unable to change to drc mode and i dont know wheter tool is working properly or...
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