how to make following code with high impedance synthesizable

[pavankumarmnnit]

hi freinds , i am having problem regarding high -Z in my design .My design is not able to be synthesized in design compiler . In my design i need to block some ports for some condition .my raw code is like below .The situation is when some port is in Z impedance some operation should be done (in dc the conditional statements are shown as error) .please suggest alternative

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bproc is
port(a,b:in std_logic_vector(2 downto 0);clk:in std_logic;sin1,sin2:inout std_logic_vector(2 downto 0):="ZZZ";
i:in std_logic_vector(1 downto 0);c,dut std_logic_vector(2 downto 0);
sftloadbar1 :inout STD_LOGIC;
testnormalbar1 :inout STD_LOGIC;
blockout1:inout std_logic;
serblocken1:inout std_logic;
serouten1:inout std_logic;
sftloadbar2 :inout STD_LOGIC;
testnormalbar2 :inout STD_LOGIC;
blockout2:inout std_logic;
serblocken2:inout std_logic;
serouten2:inout std_logic;
y:in std_logic;reconfig1,reconfig2:in std_logic;
reload:in std_logic_vector(2 downto 0));
end bproc;

architecture Behavioral of bproc is
signal k,l: std_logic:='0';
signal a1,b1:std_logic:='0';
begin
U1rocess(a,b,clk,i,sin1,sin2,y)
variable s1,s2,s3,s4:std_logic;
begin
case i is
when "00"=>s1:=a(2);s2:=b(2);s3:=sin1(2);s4:=sin2(2);
when "01"=>s1:=a(1);s2:=b(1);s3:=sin1(1);s4:=sin2(1);
when "10"=>s1:=a(0);s2:=b(0);s3:=sin1(0);s4:=sin2(0);
when others=>s1:='Z';s2:='Z';s3:='Z';s4:='Z';
end case;
if(clk'event and clk='1')then
c<=a;
d<=b;
--1st one
if(reconfig1='0' and s1='1')then
sftloadbar1<='0';
testnormalbar1<='0';
serouten1<='1';
blockout1<='1';
serblocken1<='0';
elsif(reconfig1='1' and y='0' and a1='0')then
sftloadbar1<='0';
testnormalbar1<='0';
serouten1<='1';
blockout1<='0';
serblocken1<='1';
a1<='1';
elsif(s1='0' and s3='0' and y='0')then
sftloadbar1<='1';
testnormalbar1<='1';
serouten1<='1';
blockout1<='0';
serblocken1<='0';
elsif(s1='0' and s3='0' and y='1')then
sftloadbar1<='1';
testnormalbar1<='0';
serouten1<='0';
blockout1<='0';
serblocken1<='0';
elsif(s1='0' and s3='1' and y='0')then
sftloadbar1<='1';
testnormalbar1<='0';
serouten1<='0';
blockout1<='0';
serblocken1<='0';
elsif(s1='0' and s3='1'and y='1')then
sftloadbar1<='1';
testnormalbar1<='0';
serouten1<='0';
blockout1<='0';
serblocken1<='0';
elsif(s1='1' and s3='Z' and y='0')then
sftloadbar1<='1';
testnormalbar1<='1';
serouten1<='1';
blockout1<='0';
serblocken1<='0';
elsif(s1='0' and s3='Z' and y='0')then
sftloadbar1<='1';
testnormalbar1<='0';
serouten1<='1';
blockout1<='0';
serblocken1<='1';
elsif(reload="ZZZ" and y='1') then
sftloadbar1<='0';
testnormalbar1<='0';
serouten1<='0';
blockout1<='0';
serblocken1<='0';
elsif(s1='0' and s3='Z' and y='1' and k='0')then
sftloadbar1<='0';
testnormalbar1<='0';
serouten1<='0';
blockout1<='0';
serblocken1<='0';
k<='1';
elsif(s1='0' and s3='Z' and y='1')then
sftloadbar1<='1';
testnormalbar1<='0';
serouten1<='0';
blockout1<='0';
serblocken1<='0';
elsif(s1='Z' and s3='1')then
sftloadbar1<='1';
testnormalbar1<='0';
serouten1<='0';
blockout1<='1';
serblocken1<='0';
elsif(s1='Z' and s3='0' and y='0')then
sftloadbar1<='1';
testnormalbar1<='1';
serouten1<='1';
blockout1<='0';
serblocken1<='0';
elsif(s1='Z' and s3='0' and y='1')then
sftloadbar1<='1';
testnormalbar1<='0';
serouten1<='0';
blockout1<='1';
serblocken1<='0';
elsif(s1='Z' and s3='Z')then
sftloadbar1<='1';
testnormalbar1<='1';
serouten1<='1';
blockout1<='0';
serblocken1<='0';
end if;
--2nd one
if(reconfig2='0' and s2='0')then
sftloadbar2<='0';
testnormalbar2<='0';
serouten2<='1';
blockout2<='1';
serblocken2<='0';
elsif(reconfig2='1' and y='0' and b1='0')then
sftloadbar2<='0';
testnormalbar2<='0';
serouten2<='1';
blockout2<='0';
serblocken2<='1';
b1<='1';
elsif(s2='0' and s4='1')then
sftloadbar2<='1';
testnormalbar2<='1';
serouten2<='1';
blockout2<='0';
serblocken2<='0';
elsif(s2='1' and s4='0' and y='0')then
sftloadbar2<='1';
testnormalbar2<='0';
serouten2<='0';
blockout2<='0';
serblocken2<='0';
elsif(s2='1' and s4='0' and y='1')then
sftloadbar2<='1';
testnormalbar2<='0';
serouten2<='0';
blockout2<='0';
serblocken2<='0';
elsif(s2='1' and s4='1' and y='0')then
sftloadbar2<='1';
testnormalbar2<='1';
serouten2<='1';
blockout2<='0';
serblocken2<='0';
elsif(s2='1' and s4='1' and y='1')then
sftloadbar2<='1';
testnormalbar2<='0';
serouten2<='0';
blockout2<='0';
serblocken2<='0';
elsif(s2='Z' and s4='0')then
sftloadbar2<='1';
testnormalbar2<='0';
serouten2<='0';
blockout2<='1';
serblocken2<='0';
elsif(s2='Z' and s4='1' and y='0')then
sftloadbar2<='1';
testnormalbar2<='1';
serouten2<='1';
blockout2<='0';
serblocken2<='0';
elsif(reload="ZZZ" and y='1') then
sftloadbar2<='0';
testnormalbar2<='0';
serouten2<='0';
blockout2<='0';
serblocken2<='0';
elsif(s2='Z' and s4='1' and y='1')then
sftloadbar2<='1';
testnormalbar2<='0';
serouten2<='0';
blockout2<='1';
serblocken2<='0';
elsif(s2='0' and s4='Z' and y='0')then
sftloadbar2<='1';
testnormalbar2<='1';
serouten2<='1';
blockout2<='0';
serblocken2<='0';
elsif(s2='1' and s4='Z' and y='0')then
sftloadbar2<='1';
testnormalbar2<='0';
serouten2<='0';
blockout2<='0';
serblocken2<='0';
elsif(s2='1' and s4='Z' and y='1' and l='0')then
sftloadbar2<='0';
testnormalbar2<='0';
serouten2<='0';
blockout2<='0';
serblocken2<='0';
l<='1';
elsif(s2='1' and s4='Z' and y='1')then
sftloadbar2<='1';
testnormalbar2<='0';
serouten2<='0';
blockout2<='0';
serblocken2<='0';
elsif(s2='Z' and s4='Z')then
sftloadbar2<='1';
testnormalbar2<='1';
serouten2<='1';
blockout2<='0';
serblocken2<='0';
end if;
end if;
end process U1;
end behavioral;

 

[FvM]

Re: how to make following code with high impedance synthesiz

Yes, that's pretty clear. s1,s2 et al are internal signals (respectively variables, what's the same in this reagrd), they can't be assigned a 'Z' state. 'Z' can be assigned to top level and component output ports only. In the first case, physical three-state drivers are inferred, in the second internal multiplexers.

 

[pavankumarmnnit]

Re: how to make following code with high impedance synthesiz

i am able to synthesize it in xilinx ise simulator . But unable to do in synopsys design compiler ..


Tell me clearly what modifications i should make. Regarding s1 and s2 they are stage index and they change with each stage . IN internal stages also i need to place high impedance as a one of state to in out ports...........

 

[FvM]

Re: how to make following code with high impedance synthesiz

i am able to synthesize it in xilinx ise simulator

May be. That doesn't necessarily imply meaningful operation of synthesized logic. I see, that you test the s1 and other variables for 'Z' state. This can't work. Even an INOUT port, that can be assigned 'Z' as output can't return a 'Z' value on read. This isn't an arbitrary limitation of VHDL (or Verilog) rather than a physical fact.

You have to redesign your code according to VHDL rules respectively physical properties of digital logic.

 

[vikas_33]

if u synthsize it with Xilinx tool, the trisate value would be getting changed with pull up or pull down.Please check ur xilinx Synthesis log file for more details.We can not store Z value in internal signals.

 

[pavankumarmnnit]

Re: how to make following code with high impedance synthesiz

yes they are replaced by pull ups by xilinx synthesis tool . now what should i modify code so that it can be executed in synopsys design compiler

Added after 5 minutes:

In my architecture when internal blocks gets blocked . Then i should do some operation when they are blocked . Then how to know or read that state of signals so that i can define conditional statements...........

 

[dcreddy1980]

when s2 or some other signal which you are checking for High-Z state, will also have simultaneous enable signal indicating the state of operation which can be used in your if condition.

 

[FvM]

Re: how to make following code with high impedance synthesiz

yes they are replaced by pull ups by xilinx synthesis tool

In other words, also in Xilinx the code doesn't work as expected, as previously said.

What state ever should be detected by testing the internal signal for 'Z', it must be remembered using a separate variable in the process.